CMOS

CmO)ROCARBONSANDCm.OROHYDROCARBONS - BENZYL Cm ORIDE, BENZAL Cm ORIDE AND BENZOTRICm ORIDE] (Vol 6)... 

Main memories almost exclusively consist of semiconductors on a siUcon basis in complementary metal oxide semiconductor technology (CMOS). The most important types are the pure read only memory (ROM) and the write/read memory (RAM = random access memory), which is available as S-RAM (static RAM) or as D-RAM (dynamic RAM). 

Eig. 3. Cross sections of electronics devices used in ICs. (a) NMOS transistor (b) a twin-tub CMOS device on an n-ty e substrate. 

Gate oxide dielectrics are a cmcial element in the down-scaling of n- and -channel metal-oxide semiconductor field-effect transistors (MOSEETs) in CMOS technology. Ultrathin dielectric films are required, and the 12.0-nm thick layers are expected to shrink to 6.0 nm by the year 2000 (2). Gate dielectrics have been made by growing thermal oxides, whereas development has turned to the use of oxide/nitride/oxide (ONO) sandwich stmctures, or to oxynitrides, SiO N. Oxynitrides are formed by growing thermal oxides in the presence of a nitrogen source such as ammonia or nitrous oxide, N2O. Oxidation and nitridation are also performed in rapid thermal processors (RTP), which reduce the temperature exposure of a substrate. 

Figure 9 shows a simplified fabrication sequence for an oxide-isolated -weU CMOS process that illustrates many of the essential steps used in IC manufacture. These steps are as follows ... 

Fig. 9. Fabrication sequence for an oxide-isolated -weU CMOS process, where is boron and X is arsenic. See text, (a) Formation of blanket pod oxide and Si N layer resist patterning (mask 1) ion implantation of channel stoppers (chanstop) (steps 1—3). (b) Growth of isolation field oxide removal of resist, Si N, and pod oxide growth of thin (<200 nm) Si02 gate oxide layer (steps 4—6). (c) Deposition and patterning of polysihcon gate formation of -source and drain (steps 7,8). (d) Deposition of thick Si02 blanket layer etch to form contact windows down to source, drain, and gate (step 9). (e) Metallisation of contact windows with W blanket deposition of Al patterning of metal (steps 10,11). The deposition of intermetal dielectric or final...

These processes are considerably more complex in actual CMOS fabrication. First, the lower layers of a CMOS stmcture typically have a twin-tub design which includes both PMOS and NMOS devices adjacent to each other (see Fig. 3b). After step 1, a mask is opened such that a wide area is implanted to form the -weU, followed by a similar procedure to create the -weU. Isolation between active areas is commonly provided by local oxidation of sihcon (LOCOS), which creates a thick field oxide. A narrow strip of lightly doped drain (LDD) is formed under the edges of the gate to prevent hot-carrier induced instabiUties. Passivation sidewalls are used as etch resists. A complete sequence of fabrication from wafer to packaged unit is shown in Figure 10. 

Fig. 13. (a) The CMOS inverter circuit. The FET circuit symbols emphasize that MOSFETs are actually four-terminal devices in which the / -substrate is connected to for the PFET and the -substrate is connected to the ground for the NFET. Note the conventions on drain location for the PFET and NFET. (b) Corresponding cross-sectional view roughly to scale for a 2-p.m CMOS process, where Hrepresents siUcon, Si02, polysiUcon, and ... 

Current only flows in the CMOS inverter when the load capacitor is being charged or discharged. No current flows to maintain a logic level (0 0 V, 1 5 V). Because power is dissipated only when current flows, the amount of power dissipation in a CMOS circuit is proportional to circuit... 

The lower power dissipation associated with CMOS technology makes it attractive to crowd as many FETs as possible on a chip. The remarkable increase in the number of FETs per chip has been the result of shrinking FET sizes. If the gate length, E, and width, lU, are decreased by a factor of two. 

Cryoelectronics. Operation of CMOS devices at lower temperatures offers several advantages and some disadvantages (53). Operation at Hquid nitrogen temperatures (77 K) has been shown to double the performance of CMOS logic circuits (54). In part, this is the result of the increase in electron and hole mobilities with lower temperatures. The mobiHty decreases at high fields as carrier speeds approach saturation. Velocity saturation is more important for cryoelectronics because saturation velocities increase by only 25% at 77 K but saturation occurs at much lower fields. Although speedup can... 

N. H. E. Weste and K. Eshraghian, Principles of CMOS MCSI Design, Addison-Wesley Publishing Co., Reading, Mass., 1993. 

For example, chloride and duoride ions, even in trace amounts (ppm), could cause the dissolution of aluminum metallization of complimentary metal oxide semiconductor (CMOS) devices. CMOS is likely to be the trend of VLSI technology and sodium chloride is a common contaminant. The protection of these devices from the effects of these mobile ions is an absolute requirement. The use of an ultrahigh purity encapsulant to encapsulate the passivated IC is the answer to some mobile ion contaminant problems. 

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