CMOS process

Figure 9 shows a simplified fabrication sequence for an oxide-isolated -weU CMOS process that illustrates many of the essential steps used in IC manufacture. These steps are as follows ... 

Fig. 9. Fabrication sequence for an oxide-isolated -weU CMOS process, where is boron and X is arsenic. See text, (a) Formation of blanket pod oxide and Si N layer resist patterning (mask 1) ion implantation of channel stoppers (chanstop) (steps 1—3). (b) Growth of isolation field oxide removal of resist, Si N, and pod oxide growth of thin (<200 nm) Si02 gate oxide layer (steps 4—6). (c) Deposition and patterning of polysihcon gate formation of -source and drain (steps 7,8). (d) Deposition of thick Si02 blanket layer etch to form contact windows down to source, drain, and gate (step 9). (e) Metallisation of contact windows with W blanket deposition of Al patterning of metal (steps 10,11). The deposition of intermetal dielectric or final...

Fig. 13. (a) The CMOS inverter circuit. The FET circuit symbols emphasize that MOSFETs are actually four-terminal devices in which the / -substrate is connected to for the PFET and the -substrate is connected to the ground for the NFET. Note the conventions on drain location for the PFET and NFET. (b) Corresponding cross-sectional view roughly to scale for a 2-p.m CMOS process, where Hrepresents siUcon, Si02, polysiUcon, and ... 

Chemical analysis of etching residues in metal gate stack for CMOS process... 

Many devices have been denoted to be CMOS-compatible , this term, however, not being clearly defined. In most cases CMOS-compatible means, that CMOS materials have been used, or the design can be used within a modified CMOS-process. As modifications in industrial CMOS-processes are difficult to implement, two main approaches have been pursued so far. One approach relies on an open process window... 

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

The starting material for the sensor fabrication are fully processed wafers of a 2-poly 2-metal 0.8 pm industrial CMOS process provided by austriamfcrosystems (Unterprem-statten, Austria). In the following, the main post-CMOS processing steps (schematically summarized in Fig. 4.2) are discussed. 

The membranes of the microhotplates were released by anisotropic, wet-chemical etching in KOH. In order to fabricate defined Si-islands that serve as heat spreaders of the microhotplate, an electrochemical etch stop (ECE) technique using a 4-electrode configuration was applied [109]. ECE on fully processed CMOS wafers requires, that aU reticles on the wafers are electrically interconnected to provide distributed biasing to the n-well regions and the substrate from two contact pads [1 lOj. The formation of the contact pads and the reticle interconnection requires a special photolithographic process flow in the CMOS process, but no additional non-standard processes. 

Another CMOS-process modification included the deposition of a nitride layer on the wafer backside. The backside nitride is identical with the CMOS passivation. All wafers are already delivered with this backside nitride by the CMOS foundry aus-triamicrosystems. 

The basics of the paste preparation were explained in Sect. 2.3.3. For the devices presented in this book, the paste was deposited onto cleaned chips using a dropcoating method [48,61]. The deposition was performed by the company Applied-Sensor (Reutlingen, Germany). A metal-wire loop is immersed in the paste and the tin-oxide suspension adhering to the loop forms a droplet, which is accurately positioned in the membrane center. After the drop deposition, the whole chip is put in a belt oven and annealed for 20 min at a temperature of 400 °C. This temperature is close to the elevated-temperature steps at the backend of the CMOS process. Consequently, we never observed a significant difference of the circuitry performance between coated and uncoated chips. The whole deposition process is, therefore, fully CMOS compatible, and no additional on-chip annealing is necessary. 

The standard CMOS passivation is locally opened already during the CMOS process (Fig. 4.14a). Open CMOS metallization structures serve as a contact to the Pt-wires. The thickness of the TiW-layer can be reduced to 20 nm, since there is no aluminum... 

A schematic view of the microhotplate with transistor heater is shown in Fig. 4.17 [125]. In order to ensure a good thermal insulation, only the dielectric layers of the CMOS process form the membrane. The inner section of the membrane includes an... 

The schematic of the temperature sensor on the bulk chip is shown in Fig. 5.3. The bulk chip temperature is measured via the voltage difference between a pair of diode-connected pnp-transistors (parasitic transistors as available in the CMOS process, collectors tied to substrate) working at different current densities. Transistor Qi is biased with a current of 40 pA, and transistor Q2 is biased with a current of 10 pA. 

The first device was a circular-shape microhotplate, which essentially consisted of CMOS-process materials (Sect. 4.1). The fabrication of this microhotplate required a minimum of post-CMOS processing steps. The electrochemical etching process used for the membrane release and the formation of the circular-shape Si island was optimized and can now be routinely apphed on wafer-level. 

J.A. Covington, F. Udrea, and J.W. Gardner. Resistive gas sensor with integrated MOS-FET micro hot-plate based on an analogue SOI CMOS process Proc. IEEE Conference on Sensors, Orlando, FL, USA (2002), 1389-1394. 

T. Muller, M. Brandi, O. Brand, and H. Baltes. An industrial CMOS process family adapted for the fabrication of smart sdicon sensors . Sensors and Actuators A84 (2000), 126-133. 

Polysilicon subtrates are usually encountered during MOS device fabrication for defining gate structures. For submicrometer CMOS processing, adhesion problems encountered with this substrate are even more severe. 

Thermopiles made according to standard bipolar or CMOS process can be purchased from XENSOR Integration (Delft, The Netherlands). An array of p-type silicon/Al thermocouples is connected to form a thermopile and integrated... 

Parameswaran L, Hsu C, Schmidt M. A merged MEMS-CMOS process using silicon wafer bonding. Proceedings of the IEEE International Electron Devices Meeting 1995. p 613-616. 

Poly crystalline-silicon. Mostly n-type, however, in contemporary BICMOS and CMOS processes p-type can be present as well. 

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