Gate dielectric

Gate oxide dielectrics are a cmcial element in the down-scaling of n- and -channel metal-oxide semiconductor field-effect transistors (MOSEETs) in CMOS technology. Ultrathin dielectric films are required, and the 12.0-nm thick layers are expected to shrink to 6.0 nm by the year 2000 (2). Gate dielectrics have been made by growing thermal oxides, whereas development has turned to the use of oxide/nitride/oxide (ONO) sandwich stmctures, or to oxynitrides, SiO N. Oxynitrides are formed by growing thermal oxides in the presence of a nitrogen source such as ammonia or nitrous oxide, N2O. Oxidation and nitridation are also performed in rapid thermal processors (RTP), which reduce the temperature exposure of a substrate. 

Wafer charging is becoming a critical issue as new MOS devices are designed with thinner (<10 mm) gate dielectrics. Lower energy implanters require optics that compensate for beam divergence which occurs at low energeries (32). 

The most common a-Si H TFT structure is the so-called inverted staggered transistor structure [40], in which silicon nitride is used as the gate insulator. A schematic cross section is shown in Figure 74. The structure comprises an a-Si H channel, a gate dielectric (SiN.v), and source, drain, and gate contacts. 

Facchetti A, Yoon MH, Marks TJ (2005) Gate dielectrics for organic field-effect transistors new opportunities for organic electronics. Adv Mater 17(14) 1705-1725... 

Klauk H, Halik M, Zschieschang U, Schmid G, Radlik W, Weber W (2002) High-mobility polymer gate dielectric pentacene thin film transistors. J Appl Phys 92(9) 5259-5263... 

Tri-gate transistor architechture with high-k gate dielectrics metal gates and strain engineering. Digest of Technical Papers, IEEE Trans VLSI Tech Symp 62... 

Figure 4.10. Representative og(IB)-VGS behavior of an RF-sputtered ZTO-channel TFT on (a) 40-nm A1PO and (b) 100-nm Si02 gate dielectrics on unpatterned p++ Si gate electrodes. Channel and A1 S/D contacts were defined with shadow masks. Dielectric films were annealed at 600 °C prior to channel deposition, whereas the completed stack was annealed at 300 °C. 

Carcia, R F. McLean, R. S. Reilly, M. H. 2006. High performance ZnO thin-film transistors on gate dielectrics grown by atomic layer deposition. Appl. Phys. Lett. 88 123509/1-123509/3. 

Wilk, G. D. Wallace, R. M. Anthony, J. M. 2001. High-k gate dielectrics current status and materials properties considerations. J. Appl. Phys. 89 5243-5275. 

Figure 5.12. The transfer characteristics of LTPS TFTs prepared using a solution-processed gate dielectric (bold solid line), using a solution-processed underlayer dielectric (broken line) and using a conventional process without solution processing (thin solid line), respectively. [Reproduced with permission from Ref. 24. Copyright 2007 Society for Information Display.]...

TABLE 5.3. Characteristics of TFTs with Solution-Processed Gate Dielectric and Underlayer Dielectric... 

Next, we fabricated TFTs whose ULD, channel Si, and gate dielectric were all solution-processed. The fabricated TFTs (TFT-4, 5, and 6) have similar solution-processed 50-nm-thick silicon films,1011 the details of which are described in Section 5.4. In addition, TFT-4 (n-channel) and TFT-5 (p-channel) have the SP-Si02 as both ULD and gate dielectric, which are fabricated using... 

Nishikawa, Y. Yamaguchi, T. Yoshiki, M. Satake, H. Fukushima, N. 2002. Interfacial properties of single-crystalline Ce02 high-k gate dielectrics directly grown on Si (111). Appl. Phys. Lett. 81 4386 1388. 

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