Single crystalline silicon and CMOS

Traditional FET transistors are fabricated on a single ciystalline silicon wafer of a few hundred micrometer thickness. The silicon crystalline framework is homogenous and continuous with very low levels of defects. The electron mobility,, is therefore at a high level, ranging from few hundreds to over a thousand cm s, enabling 

Driven by the microelectronics industry, the CMOS fabrication process has been continuously refined to make smaller MOSFETs, which are both faster and more cost-efficient. The state-of-the-art 

Despite the high performance of CMOS, its manufacturing process requires very high-cost equipment, clean room facilities, and expensive high purity single-crystal silicon wafers. Those limitations have set up the barrier to further reduce the fabrication costs and hindered the use of CMOS technology in large area electronics such as displays. 

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