Gate length

The lower power dissipation associated with CMOS technology makes it attractive to crowd as many FETs as possible on a chip. The remarkable increase in the number of FETs per chip has been the result of shrinking FET sizes. If the gate length, E, and width, lU, are decreased by a factor of two. 

A popular metric of the speed performance of a EET is, the maximum frequency of unity current gain (49). Eor short gate length devices operating at the saturated velocity this metric can be expressed as follows, where... 

Figure 13.11. High-frequency behavior of TFTs built with semiconductor wires and ribbons, (a) xs-Si MOSFETs on PI substrates. (Reprinted with permission from Ref. 17. Copyright 2006 IEEE) (b) xs-GaAs MESFETs on PET substrates, (c) Dependence of fT on gate length of xs-GaAs MESFETs. The different symbols represent measurements on different devices the dashed line corresponds to calculation. (Reprinted with permission from Ref. 82. Copyright 2006 American Institute of Physics.)...

The saturation current is denoted /sd,sat> the effective mobihty and the capacitance of the gate oxide Cox- The effective geometrical parameters of the transistor include its overall gate width, W g, and the effective gate length, Leff. 

As the integrated circuit (IC) industry has chosen chemical mechanical planarization (CMP) as one of the indispensable processes in the generations of transistor gate lengths equal to or smaller than 0.35/im, it is imperative that the CMP-related process problems be investigated and... 

Fig. 39 (a) Device schematic of the dual-gate graphene transistor, (b) SEM image of a doublechannel graphene transistor. The channel width is 27 pm, and the gate length is 350 nm for each channel. (Reprinted with permission from [298])... 

Although transparent substrates allow the use of a self-aligned process (Asama et al 1983), it is difficult to work with gate lengths below 5 fim, especially in large-area devices. Thus L is essentially a fixed number and W is adjusted to satisfy the electrical requirements in the ON state. 

FIG. 6.1. Schematic diagram of the thin film transistor using an -6T polymer for the active layer [155]. Gold source and drain pads are fabricated using the photolithographic technique. The gate length varied between 2.5 and 150 nm and the width was 250 pm. The polymer (from 2.5 to 150 nm thick) is sublimed over the contacts. 

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