CMOS design

In order to illustrate exactly what we are discussing, the following diagram of a CMOS design used in 1997 is presented on the following diagram. That is, ap-type silicon source is formed on an n-type well, and vice-versa. 

N. Weste and K. Eshraghian, Principals of CMOS Design, Addison-Wesley Pub. Co., Reading, MA (1985). 

CMOS ICs utilize both NMOS and PMOS devices. Starting with a p-substrate, the NMOS would be fabricated on the p-substrate and the PMOS in an -weU, and vice versa. With the addition of an n-well, p-well or twin tub process, CMOS fabrication is similar to that for NMOS, although more complex. Table 8.4 (Fabricius, 1990) shows the Mead-Conway scalable CMOS design rules. The dimensions are given in multiples of k and the rules are specified by the MOS Implementation System (MOSIS) of the... 

TABLE 8.4 MOSIS Portable CMOS Design Rules... 

Fier, D.R and Heikkila, W.W. 1982. High performance CMOS design methodologies. In Proceedings IEEE Custom Integrated Circuits Conference, pp. 325-328. Rochester, NY. 

These processes are considerably more complex in actual CMOS fabrication. First, the lower layers of a CMOS stmcture typically have a twin-tub design which includes both PMOS and NMOS devices adjacent to each other (see Fig. 3b). After step 1, a mask is opened such that a wide area is implanted to form the -weU, followed by a similar procedure to create the -weU. Isolation between active areas is commonly provided by local oxidation of sihcon (LOCOS), which creates a thick field oxide. A narrow strip of lightly doped drain (LDD) is formed under the edges of the gate to prevent hot-carrier induced instabiUties. Passivation sidewalls are used as etch resists. A complete sequence of fabrication from wafer to packaged unit is shown in Figure 10. 

A. Frey, M. Jenkner, M. Schienle, C. Paulus and B. Holtzapfl, Design of an Integrated Potentiostat Circuit for CMOS Bio Sensor Chip, IEEE, 2003, pp. 9-12. 

Many devices have been denoted to be CMOS-compatible , this term, however, not being clearly defined. In most cases CMOS-compatible means, that CMOS materials have been used, or the design can be used within a modified CMOS-process. As modifications in industrial CMOS-processes are difficult to implement, two main approaches have been pursued so far. One approach relies on an open process window... 

The third microhotplate introduced in Sect. 4.3 was designed to extend the operation temperature limit imposed by the CMOS-metallization contacts in the heated area. A new heater design was devised, and a microfabrication sequence that enables the realization of Pt temperature sensors and Pt-electrodes was developed. This microhotplate was also monolithically integrated with circuitry as presented in Sect. 5.2, and operating temperatures of up to 500 °C have been achieved. 

A shadow-mask technique has been applied for the local metal deposition to exclude metal residues on other designs processed on the same wafer (Fig. 4.2b). Such metal residues may be caused by imperfections in the patterned resist due to topographical features on the processed CMOS wafers or dust particles. The metal film is only deposited in those areas on the wafer, where it is needed for electrode coverage on the microhotplates. This also renders the lift-off process easier since no closed metal film is formed on the wafer, so that the acetone has a large surface to attack the photoresist. Another advantage of the local metal lift-off process is its full compatibility with the fabrication sequence of chemical sensors based on other transducer principles [20]. 

A novel microhotplate design was proposed to overcome the CMOS operating temperature limit and to avoid polysilicon-induced drift problems. A cross-sectional schematic of the device is shovm in Fig. 4.11. Instead of using a polysilicon resistor as temperature sensor, a platinum temperature sensor is patterned on the microhotplate. The Pt-metallization process step was used to simultaneously fabricate the electrodes and the temperature sensor. The CMOS-Al/Pt contacts are located off the membrane... 

The central topic of the book was the integration of microhotplate-based metal-oxide gas sensors with the associated circuitry to arrive at single-chip systems. Innovative microhotplate designs, dedicated post-CMOS micromachining steps, and novel system architectures have been developed to reach this goal. The book includes a multitude of building blocks for an application-specific sensor system design based on a modular approach. 

The main goal of another microhotplate design was the replacement of all CMOS-metal elements within the heated area by materials featuring a better temperature stability. This was accomplished by introducing a novel polysilicon heater layout and a Pt temperature sensor (Sect. 4.3). The Pt-elements had to be passivated for protection and electrical insulation, so that a local deposition of a silicon-nitride passivation through a mask was performed. This silicon-nitride layer also can be varied in its thickness and with regard to its stress characteristics (compressive or tensile). This hotplate allowed for reaching operation temperatures up to 500 °C and it showed a thermal resistance of 7.6 °C/mW. 

F. Udrea, J.W. Gardner, D. Setiadi, J.A. Covington, T. Dogaru, C.C. Lua, and W.l. MUne. Design and simulations of SOl-CMOS micro-hotplate gas sensors . Sensors and Actua-torsB78 (2001), 180-190. 

When designing digital circuits we are usually concerned with the rise and fall times of the design, given device tolerances. The example given here is for a CMOS inverter, but the procedure used can be applied to any switching circuit with device tolerances. Wire the circuit below ... 

Nominal 3.6 V batteries have been designed for direct mounting on printed circuit boards for CMOS and NMOS memory support applications. Such cells are normally float charged from the main microcomputer DC power supply and constitute a form of uninterruptible power supply (UPS). 

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