Field oxide

Step 4. A thick Si02 layer (the field oxide) is grown over the -chanstop to isolate the device. This also drives the p -region deeper into the substrate. 

Step 8. The -type source and drain regions are created by As ion implantation. The As can penetrate the thin gate oxide, but not the thick field oxide or the polysihcon gate. The formation of the source and gate does not require a separate resist pattern, thus this technique is called self-aligning. 

Fig. 9. Fabrication sequence for an oxide-isolated -weU CMOS process, where is boron and X is arsenic. See text, (a) Formation of blanket pod oxide and Si N layer resist patterning (mask 1) ion implantation of channel stoppers (chanstop) (steps 1—3). (b) Growth of isolation field oxide removal of resist, Si N, and pod oxide growth of thin (<200 nm) Si02 gate oxide layer (steps 4—6). (c) Deposition and patterning of polysihcon gate formation of -source and drain (steps 7,8). (d) Deposition of thick Si02 blanket layer etch to form contact windows down to source, drain, and gate (step 9). (e) Metallisation of contact windows with W blanket deposition of Al patterning of metal (steps 10,11). The deposition of intermetal dielectric or final...

These processes are considerably more complex in actual CMOS fabrication. First, the lower layers of a CMOS stmcture typically have a twin-tub design which includes both PMOS and NMOS devices adjacent to each other (see Fig. 3b). After step 1, a mask is opened such that a wide area is implanted to form the -weU, followed by a similar procedure to create the -weU. Isolation between active areas is commonly provided by local oxidation of sihcon (LOCOS), which creates a thick field oxide. A narrow strip of lightly doped drain (LDD) is formed under the edges of the gate to prevent hot-carrier induced instabiUties. Passivation sidewalls are used as etch resists. A complete sequence of fabrication from wafer to packaged unit is shown in Figure 10. 

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

The H202-based slurry performed the best in this evaluation. However, it has problems with plug recess and field oxide erosion. 

To measure the final oxide thickness in the PMD process, the measurement sites can be set up over field oxide or over the polysilicon interconnections (see Fig. 6). However, since there are fewer variables in measuring over the field oxide, and the field oxide process is relatively well established, the PMD thickness is more accurately measured over the field oxide. If the measurement is over the polysilicon, the resultant PMD thickness measured can be affected by the deposited polysilicon thickness, the polysilicon doping, and the field oxide thickness variation, while if the measurement is over the field, the PMD thickness is affected only by the field oxide thiekness. 

For the ILD process, it is less feasible to continue measuring over field oxide, because multiple oxide layers are present (also see Fig. 6). The true thickness and thickness uniformity of the particular level of an ILD proeess can be confounded by the presence of the underlying previous layers. Thus, after the first metal process, it is preferable to measure the oxide thickness directly on a metal line. 

A thick (> 1 jum) field oxide layer is formed after the implant activation. The field oxide is generally deposited nsing low-pressnre CVD (LPCVD) or plasma-enhanced CVD (PECVD) process becanse the Si-face of SiC has very low oxidation rate and becanse consumption of the implanted layer must be minimized. The field oxide layer is then patterned by selectively etching to remove all oxide from the... 

A 3/8 inch diameter aluminum or titanium-tungsten dot pattern WLs fabricated on top of the cured polyimide film to make electrical leakage to substrate measurements for pinhole density estimation. An etch decoration technique was used to visually determine pinhole densities in polyimide films. The polyimide film was cast on substrates comprised of a layer of 200 nm thick alumimmi on blue colored field oxide with a grid pattern for area computation. Replicate holes were etched in the aluminum by a hot phosphoric acid solution. With the polyimide film removed, a good visual contrast was achieved for pinhole density counting. 

The results of semi-quantitative charge spreading tests suggests that the lateral conductance of polyimide-field oxide interfaces can be sufficiently low to permit reliable device operation. This topic must be addressed in the context of the overall processing of the interface, including any adhesion promoters used. 

Figure 22 Creep-up phenomena onto (a) field oxide and (b) the wall of contact hole.29...

One of the main motivations for the development of the STI process is to eliminate the bird s beak phenomenon. With STI, the field oxide is well embedded into the Si and is clearly distinctive from the active-area regions. It allows very narrow active-area pitches and a higher device-packing density. 

The variation in the field oxide recess was examined on six consecutive lots (25 wafers per lot) polished with HSS and LSS. It was observed that the HSS provided a more consistent field oxide recess from lot to lot, wafer to wafer, and within wafers as shown in Fig. 13.8. 

FIGURE 13.8 Relative thicknesses (with respect to zero overpolishing) of the remaining field oxides measured from six successive lots after being polished by HSS and LSS, respectively. 

Figure 8.3 shows a LOCOS isolation process to grow the field oxide. Such a process leads to enlargement of the field region due to oxidation continued beyond the originally... 

For simplicity and to understand the STI mechanism, we introduce the following assumptions. First, the planarization length is zero, that is, there is no interaction between removal rates of patterned and blanket areas, and second, there is no dishing or recess at field oxide between active silicon nitrides in feature size level. On the basis of the above assumptions, STI CMP procedures can be divided into four steps as showm in Fig.2. The first step is defined as the period in which initial step heights of patterned area are perfectly eliminated. At this stage then erosion is generated due to the difference of removal rate between patterned and blanket area as showm in Fig.2(b). The second step is defined as the period in which the fully planarized oxide surface of patterned area is polished to expose the silicon nitride top surface. 

L. K. White, Bilayer taper etching of field oxides and passivation layers, J. Electrochem. Soc. 132, 1705, 1985. 

Figure 7. AES survey spectra from defect particle (left) and adjacent field oxide (right).

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