Implanters used in CMOS Processing

The various implants are typically serviced by distinct types of tools, each engineered to provide a solution for a specific segment of the implant application space. Traditionally, these segments have been called high current, medium current, and high energy, and can be characterized mainly by the dose and the energy of implanted ions. 

Medium current implantation typically refers to doses in the 1011—1014 cm 2 range at maximum energies of several hundred keV and as low as 3 keV. The most common applications for which medium current implanters are used include threshold voltage adjustment halo or pocket implants field isolation and channel engineering. 

It should be noted that there is substantial applications overlap among the implantation segments. For example, medium current systems can run high dose source drain implants for pilot lines, albeit at low throughput. High energy 

---

The typical thin films that are deposited include semiconductors (e.g., polysilicon), insulators (e.g., silicon nitride), and metals (e.g., aluminum). In addition, some layers are grown (oxide), diffused, or implanted (dopants) rather than deposited using thin-film techniques. A cross section of a complementary metal oxide semiconductor (CMOS) process that includes six levels of metal is shown in Figure 1.2 [1]. A schematic diagram of one of the first MEMS devices, which used semiconductor processing for fabrication, the resonant gate transistor, is shown in Figure 1.3 [2]. 

These processes are considerably more complex in actual CMOS fabrication. First, the lower layers of a CMOS stmcture typically have a twin-tub design which includes both PMOS and NMOS devices adjacent to each other (see Fig. 3b). After step 1, a mask is opened such that a wide area is implanted to form the -weU, followed by a similar procedure to create the -weU. Isolation between active areas is commonly provided by local oxidation of sihcon (LOCOS), which creates a thick field oxide. A narrow strip of lightly doped drain (LDD) is formed under the edges of the gate to prevent hot-carrier induced instabiUties. Passivation sidewalls are used as etch resists. A complete sequence of fabrication from wafer to packaged unit is shown in Figure 10. 

Ion implantation has become the dominant doping technique, particularly in the fabrication of bipolar-CMOS devices and in the formation of shallow junctions. Laser ablation sampling coupled with ICP-MS was applied recently to the determination of total dopant dose. Since this technique spatially and temporally separates the sampling and ionization steps, it has the potential to produce more quantitative results than SIMS for trace elements in a given matrix. Wafer surface analysis can also be used to monitor the contamination induced hy different process steps. The importance, in terms of contamination contrihution, of the chamber components used for film deposition and ion implantation was demonstrated, as was the effect of cleaning bath solution purity. ... 

---