Pipeline architecture

Pipeline architecture A computer architecture that employs time-sequential parallelism rather than spatial parallelism. That is, the input data is time sequenced, and each processor performs one portion of the total operation on each piece of data in time sequence. 

That SPAs can have both electrical I/O as well as optical I/O renders them potentially useful to any application that interfaces between optical and electronic realms. Such applications are more numerous than already discussed in this section. The emerging SPA technology will likely result in new applications emerging for years to come. Some additional applications not previously mentioned are the parallel-processing planes of pipeline architectures (useful for pixel-level image processing) the various levels of optical neural networks the input, filter, and/or output planes of optical correlators and optical phased-array beam steering. 

Richard Hartley and Albert E. Casavant, "Tree-Height Minimization in Pipelined Architectures , Proc. of ICCAD 89, pages 112-115, November 1989. 

K. McNall and A. Casavant, Automatic Operator Configuration in the Synthesis of Pipelined Architectures, in 27th Design Automation Cotference, pp. 174-179, 1990. 

Figure 8.23 shows the five-stage pipeline architecture of the hardware architecture to measure the inteifacial tension. The five pipeline stages have the following tasks [68] ... 

Slides Covering pipelines with polymeric films cathodic protection of pipelines, ships, etc.. With zinc bracelets use of inert polymers in chemical plant galvanic corrosion in architecture (e.g. A1 window frames held with Cu bolts) weld decay. 

There are other architecture patterns, one of which is Pipe and Filter (Buschmann et al 1996). Pipeline Pilot of SciTegic (now part of Accelrys) is a good application of the Pipe and Filter Pattern and is widely used in the chemical information domain. 

Information and communication systems strategy designated ICSS - for oil and gas distribution pipelines is based on a system architecture that includes four components ... 

The architecture of the machine can be divided into three sections generators, modifiers and delay memory. Each section is pipelined and does not share hardware with the other sections. The pipeline timing for generators is detailed below in Table 5.5 ... 

The TMS320C30 [Papamichalis and Simar, 1988] follows the basic architecture of the TMS-320 series. Unlike the DSP-32, it uses pipeline interlocks. Like the DSP-32, it features its own internal format for floating point numbers. Because of the four stage pipeline organization, it can perform a number of operations in parallel. It also features a delayed branch - something of a novelty in DSP processors. The TMS320C40 [Simar et al., 1992] has six parallel bidirectional I/O ports controlled by DMA on top of the basic TMS-320C30 architecture. These ports have been used for multiprocessor communication. 

Computer architectures have evolved over the years from the classic von Neumann architecture into a variety of forms. Great benefits to operating speed have accrued. The major contributions to speed have been the introductions of parallel processors and of pipelining. For many years, these innovations were transparent to the programmer. For example, to program in Fortran to run on a CDC 6600 (10, one did not take cognizance of the existence of multiple functional units, nor did one consider the I/O channels when writing Fortran applications for the IBM 360 series (2). This was because the parallel processors were hidden behind appropriate hardware or software. 

Any machine with virtual memory suffers performance degradation when page swaps are too frequent. Some pipelined machines like the TI-ASC (3) or the CDC Star-100 (4) have rather long setup times for their arithmetic pipes. Multiprocessor machines like the Illiac IV (5) are next to useless if the programmer pays no attention to the architecture. These features all directly impact the user they have not been effectively hidden by software at any level. Improvement of this situation could result if compilers took on the burden of optimizing code so as to promote efficient hardware utilization. 

The Tavema Project11 is an example of a domain-aware workflow toolkit that helps to define and perform these biological analyses and transformations. Tavema can handle both proprietary and XML-based data formats and uses XML itself to describe the workflows and data format transformations. Tavema also supports Web Service Definition Language (WSDL) and Web Services integration to exploit a services-oriented architecture when executing workflows, like the one described here. The services orientation that Tavema is built around works well with the services-based architecture presented here. Because Tavema interfaces with services (both informatics services and grid services like resource managers and security services), it is well suited for construction of the kinds of complex research pipelines common in bioinformatics research. 

Pipeline Pilot is deployed as a client/server system, with desktop PCs connecting to a central service-oriented architecture deployed on an Apache Web server. The server maintains a repository of components and protocols, in addition to its role as a computational engine. Jobs are spawned to run protocols and provide feedback to the client. These facilities are exposed as standard Web services. 

More limited versions of SIMD architectures are common today. Rather than simultaneously computing all results as is done in the CM-2, the more modern SIMD architectures pipeline data through one or more execution units and can achieve high computational rates due to the repetitiveness of the work involved. This arrangement is used in vector processors (for example, the Cray XI ). Also, modern microprocessors now have extensions allowing single instructions to perform identical operations on multiple pieces of data. Examples include Intel s Streaming SIMD Extensions (SSE) and Motorola AltiVec used in recent versions of the IBM POWER processor. 

This chapter focuses on supply chain structure and ownership, one of the Cs in the supply chain framework. The chain structure is the backbone or the pipeline through which information and material flow in the supply chain. It is the process map of a supply chain that typically crosses many independent company boundaries. Once a supply chain map is generated, the location of entities, as well as ownership, and the connections to the rest of the supply chain architecture influence the observed lead times, costs, incentives, and thus performance, of the supply chain. 

The case study processor used in this work is based in the Microprocessor without Interlocked Pipeline Stages (MIPS) architecture. It has a standard processor architecture based on the Reduced Instraction Set Computing (RISC) instmction set. The basic idea behind RISC is to use simple instructions, which enable easier pipelining and larger caches, while increasing its performance. The MIPS architecture can be seen since 1985 in commercial applications, from workstations to Windows CE devices, routers, gateways and PlayStation gaming devices. 

As another alternative, one can use checkers as a hardware-based technique. An architecture called DIVA was proposed in Austin (1999), using a simple functional checker to verily the correctness of all computation being executed in the main processor. The technique added a functional checker to the execution stage of the pipeline, so that it allowed only correct resrtlts to reach the register barrier. The implementation of the checker was done so that it was simpler than the core processor, since it received the instraction to be executed together with the values of the input operands and the result from the main processor. By doing so, the checker did not have to care about address calcrrlations and therefore could be implemented in a simpler way than the processor core. 

We have presented a refinement-based proof-method for the verification of modern processor architectures, and demonstrated its applicability by showing the correctness of a data-path involving multiple functional units, registerrenaming, dynamic scheduling, and out-of-order execution, thus significantly exceeding the complexitiy of static pipelines as e.g. treated in [BD94]. Still, this work needs to be extended in a number of ways. 

ABSTRACT The paper presents a decision support system (DSS) for evaluation of risk pipeline risk. The system is able to support risk assessment and risk ranking of sections of natural gas pipelines. The DSS uses an architecture based on a data base, a model base and user interface. The model base has been built based on Multi-Attribute Utility Theory. The multi-attribute approach analysis risks in three dimensions of impact. These dimensions are human, financial and environmental impact. The way in which the model translates decisionmakers preferences into risk management decisions is highlighted. The paper presents the DSS, including some dialogue modules of the system based on real appUcations. 

This last property is useful for studying pipelined or multithreaded architectures. Together with the more flexible I/O, it compares favorably with the otherwise resembling approach of SiL [11],... 

The systolic answer to the problem is to localize the broadcasts in the DG before scheduling and mapping its nodes [15], so as to synthesize an architecture where all communications are made local. Such a derivation process is well understood. Some recent synthesis results are discussed in chapter 6. The natural idea is to replace the broadcast of a variable by its pipelined propagation along the direction of the dependence vector. In this way, we obtain the DG of figure 3. 

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