Execution unit

The rest of this chapter deals with how to model and specify components executable units that can be plugged together with different interaction schemes connecting them. Our modeling approach is based on the ideas put forth in three definitions. 

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More limited versions of SIMD architectures are common today. Rather than simultaneously computing all results as is done in the CM-2, the more modern SIMD architectures pipeline data through one or more execution units and can achieve high computational rates due to the repetitiveness of the work involved. This arrangement is used in vector processors (for example, the Cray XI ). Also, modern microprocessors now have extensions allowing single instructions to perform identical operations on multiple pieces of data. Examples include Intel s Streaming SIMD Extensions (SSE) and Motorola AltiVec used in recent versions of the IBM POWER processor. 

As shown in figure 1, behavioral synthesis starts with two kinds of information a behavioral description and an external library of functional units (FUs). The external library of FUs may include standard execution units (adders, multipliers, ALUs, etc.) as well as more complex units defined by the designer. These may be large, complex blocks such as cache memories, I/O units, and so on. 

A CATHEDRAL-II-generated data path is built from a set of six execution units (EXUs), as well as a set of memories, I/O units, and controller modules. The EXUs include an ALU / shift unit, an address computation unit, a parallel multiplier / accumulator, a parallel / serial divider, a comparator, and a normalizer-scaler, and are composed of adders, shifters, etc. 

Execution Unit Organization Analysis This phase analyzes the behavior and calculates various parameters such as data width, address width, external data bus width and external address bus width. The relationship between these parameters is used to determine how the execution unit should be organized. Execution unit organization analysis is described in Section 7.3. In contrast, EMUCS does not perform a similar analysis. This task is necessarily specific to the microprocessor because in the general case, separate address and data sections cannot be assumed. 

Expression Context Analysis This phase analyzes each expression in the behavior and determines how it is used in relation to the expressions surrounding it. For instance, the result of an expression may be used only as a memory address. This information is recorded and used later by a synthesis phase to assign an appropriate type of register to the expression. As for Execution Unit Organization Analysis, this phase is specific to microprocessor design. 

Code Generation Code generation maps the expressions and procedures at the behavioral level to a list of uncompacted control sequences and a network of symbolic units using a rule base to select alternative ways to synthesize each behavioral expression. Symbolic busses are also generated in this phase. The rule base is selected based on the information recorded by the execution unit organization analysis phase. Code generation is described in detail in Section 7.4. 

Current technology limits the number of global busses to only two or three. Most contemporary commercial microprocessors use two busses. The choice of a two bus scheme has the advantage that dense two-output register cells can be used. This allows busses to be routed directly over functional units and registers in the execution unit because each register can be connected to both busses. The current implementation of SUGAR only understands 2-bus execution units. 

SUGAR determines the number of processing sections in the execution unit based on the following two factors ... 

The code generation algorithm generates code by using a local pattern matching technique to match a library of templates against subtrees in the behavioral description. There is one template library for each type of execution unit, where the type of the execution unit is determined by the number of processing sections in it. 

The fixed bus models used in SUGAR assume that the execution unit is partitioned into processing sections that contain local functional units and local registers. The communication between the processing sections is organized in such a way that maximum parallelism can be achieved only if the functional units access registers local to their... 

Determine for each symbolic bus what execution unit processing sections are used to move data. 

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