Hardware-Based Techniques

In order to provide reliable systems that can cope with radiation effects, we believe that the solution hes in combining software-based and hardware-based techniques. The main objective of this book is finding the best trade-off between software-based and hardware-based techniques, in order to increase existing fault detection rates up to 100%, while maintaining low overheads in performance by means of operating clock frequency and application execution time, and in area by means of program and data memory overhead, and extra hardware modules. 

Fault tolerance techniques aiming to detect transient effects can be mainly divided in three broad categories (1) software-based techniques, (2) hardware-based techniques and (3) l brid techniques. Fault tolerance techniques can be applied at different levels of implementation, starting from the software level down to the architecture description level, the logical and transistor level, until the layout level. In this book, we will focus on hybrid techniques applied at software level. 

Hardware based techniques can be based on duplication with comparison, ED AC codes to protect registers and some other logical parity techniques to protect the logic. But all of them have some limitation on fault detection coverage. Without duplicating the whole processor, hardware-based techniques cannot achieve full... 

Hybrid techniques combine softw are-based techniques with hardware-based techniques. The design space for hybrid techniques is quite large, since it multiplies all hardware-based possibihties per the software-based options. 

The result from the use of hybrid techniques is high efficiency, since they can provide a high level of confiability while minimizing the introduced overhead. They also offer low development time (from the software-based techniques) and small performance degradation (from the hardware-based techniques). As drawbacks, they requite the application source code (in order to transform it), which is not always available, and require changes, at least, in the system s architecture. 

Hardware-based techniques must be implemented during the design phase. Because of that, such techniques cannot be applied to COTS processors or restricted IPs targeted at the general purpose market. Their use is mainly restricted to ASICs or... 

As an alternative to time and space redundancy, hardware-based techniques offer monitoring blocks. The second group of techniques adds special hardware mod-... 

As another alternative, one can use checkers as a hardware-based technique. An architecture called DIVA was proposed in Austin (1999), using a simple functional checker to verily the correctness of all computation being executed in the main processor. The technique added a functional checker to the execution stage of the pipeline, so that it allowed only correct resrtlts to reach the register barrier. The implementation of the checker was done so that it was simpler than the core processor, since it received the instraction to be executed together with the values of the input operands and the result from the main processor. By doing so, the checker did not have to care about address calcrrlations and therefore could be implemented in a simpler way than the processor core. 

As stated in the previous Chapters, software-based techniques are unable to detect all faults affecting the control flow, while hardware-based techniques cannot protect processors without at least doubling its area. On the other hand, combined into hybrid techniques, they can not only present increase their detection rates, but also be optimized into achieving a better tradeoff between area overhead and performance degradation, and fault detection. 

In order to detect such errors, PODER uses the communication between software-based techniques and hardware-based techniques. It does so by calculating a second signature for each BB, called XOR, during compilation time (by the software-based techniques), and during runtime (by the hardware module). The XOR value equals to the result of the operation exclusive OR (XOR) between all the instmctions from the BB. 

OCFCM itself is defined as a non-intrasive hardware module and therefore corrld be considered a pure hardware-based technique. Irrstead, OCFCM alone cannot achieve its main objective, which is detecting control flow errors. To do so, it has to be complemented by the Inverted Branches software-based technique (described in Sect. 4.3) and configured by the apphcation running in the processor. Because of these characteristics, it is considered as a hybrid farrlt tolerant technique, even if not as tightly coupled with the software-side as PODER. 

OCFCM s hardware-based side aims at detecting faults that cause incorrect deviations in the execution program s flow. In order to do that, the hardware module combines most of the non-intrusive hardware-based techniques, such as checking if the processor is accessing correct memory areas for data and program, the consistency of some variables, control flow checkpoints, and also the PC evolution during runtime. 

Such results show that VAR and BRA combined with PODER can be used in harsh environments and allow designers to reach fast fault diagnosis and correction. When comparing to hardware-based techniques, such as TMR, we can notice an area reduction higher than 66 % and still acceptable fault coverage of 98.3 %. On the other hand, the hardened application takes 2.34 times the original execution time and requires 15 % extra area for the hardware module. 

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