Bonding wire

The most widespread process for electrically contacting bare silicon chips is wire bonding. This applies in particular to areas of application characterized by high climatic and mechanical requirements because of the flexibility of the wire bonds. 

The first step is to locate the silicon chip mechanically on the substrate with an adhesive. Adhesives with a conductive filler are often used, because their good thermal conductivity helps in removing process heat. The conductive adhesive has to be chosen firstly for high mechanical strength and secondly for temperature stability matched to the application. Application can be by dispensing, pin transfer, or stenciling, although this third option is only conditionally suitable for 3D-MID. 

The space needed by the bond head during the process is another aspect that has to be taken into account for US wire bonding on 3D-MID. Deep-access bond heads of some types can bond inside recesses. This permits a high level of 3D design freedom. On the horizontal plane, approximately 1.2 mm of clearance is typically required between the second bond and the next raised object (component, MID wall, etc.). 

Ultrasonic wire bonding on MID has to allow for other factors influencing bond-ability that are of minor significance at best in the context of conventional printed-circuit boards or ceramic substrates. For example, the thickness of the plating, metallization surface roughness, and the type of substrate structuring are all of crucial importance. With two-shot MID the structural design and the mechanical 

FIGURE 5.20 Die bonding in a cavity to reduce the distance between chip and substrate surface [48] 

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Fig. 3. Plastic package with wire bond interconnect (3).

Wire Interconnect Materials. Wire-bonding is accompHshed by bringing the two conductors to be joined into such intimate contact that the atoms of the materials interdiffuse (2). Wire is a fundamental element of interconnection, providing electrical connection between first-level (ie, the chip or die) and second-level (ie, the chip carrier, or the leadframe in a single-chip carrier) packages. 

Characteristics of the wire materials, which are cmcial to the strength of the wire bond, include wire dimensions, tensile strength, elongation, and... 

J. Hirota and co-workers, "The Development of Copper Wire Bonding for Plastic Molded Semiconductor Packages," 35th Electronic Component Conference Proceedings,S3J2Lshm.g. on,E).Q. 1985, pp. 116—121. 

The last technique commonly employed to deposit metals for compound semiconductors is electroplating (150). This technique is usually used where very thick metal layers are desired for very low resistance interconnects or for thick wire bond pads. Another common use of this technique is in the formation of air-bridged interconnects (150), which are popular for high speed electronic and optoelectronic circuits. 

Multilayer boards, which use multiple interior laminates of plastic and copper, now comprise over half of the value of production, though much less on a surface area basis. Surface mount technologies demand extreme flatness and reproducibiHty from surfaces. Greater packing density has led to commercial production of finer lines and holes, often less than 50 p.m and 500 p.m, respectively. Electroless gold over electroless nickel—phosphoms, or electroless nickel—boron alone, is often used as a topcoating for wire bonding or improved solderabiHty. 

Wire Bond - each die mounting is bonded, both electrically and physically... 

One of the first applications of the new mesh and node intramolecular circuit rules discussed above is the well-known problem in electrical circuit theory of the balancing of a Wheatstone bridge. In Fig. 21, a molecular Wheatstone bridge is presented, made of loop-like 4 tolane molecular wires bonded via benzopyrene end-groups for nano-pads 1 and 3, and via pyrene end-groups for nano-pads 2 and 4. This four-electrode and four-branch molecule is connected to a battery and an ammeter. 

Wire bonding, 9 694-695 Wire coating extrusion, 19 548-549 Wire, extrusion of, 19 790 Wire insulation HDPE, 20 174-175 LLDPE, 20 208-209 Wire interconnect materials... 

The last and most advanced system presented in this book includes an array of three MOS-transistor-heated microhotplates (Sect. 6.3). The system relies almost exclusively on digital electronics, which entailed a significant reduction of the overall power consumption. The integrated C interface reduces the number of required wire bond connections to only ten, which allows to realize a low-prize and reliable packaging solution. The temperature controllers that were operated in the pulse-density mode showed a temperature resolution of 1 °C. An excellent thermal decoupling of each of the microhotplates from the rest of the array was demonstrated, and individual temperature modulation on the microhotplates was performed. The three microhotplates were coated with three different metal-oxide materials and characterized upon exposure to various concentrations of CO and CH4. 

Figure 16.1 A bundle of parallel wires bonded with grain-boundary segments. An...

Figure J shows an example of the top surface features of an MCP designed for electrooptical-signal-processing applications (33). The MCP has 18 chip attach pads surrounded by dumbbell-shaped pads for wire bonding and repair. The top surface also contains off-package I/Os along two sides, wide power distribution lines, and sites for decoupling capacitors. In this design, the package size of 2.25 by 2.25 in. (5.7 by 5.7 cm) was determined by the top-layer features rather than by the maximum interconnection density.

Additional delay may be imposed by the capacitive loading of branch lines, receivers, and bonding pads attached to the interconnection or by the series inductance of vias or wire bonds. If the additional capacitance can be assumed to be uniformly distributed over the interconnection with electrically short spacing (an assumption that is not always valid), the modified propagation delay (Tpd ) is given by (37)... 

Modeling of High-Speed Interconnections. Modeling the electrical behavior of an interconnection involves two steps. First, the transmission line characteristics, such as the characteristic impedance, propagation constant, capacitance, resistance, dielectric conductance, and coupling parameters, must be calculated from the physical dimensions and material properties of the interconnection. In addition, structures, such as wire bonds, vias, and pins, must be represented by lumped resistance (R), inductance (L), and capacitance (C) elements. 

The top metal layer in TFML structures must be compatible with bonding and assembly processes. Gold, with an underlying barrier metal such as TiW or Ni, is usually patterned over the top metal layer for oxidation protection and wire-bonding compatibility. For solder-bonding processes, a very thin layer (<100 nm) of gold is deposited over a solderable metal such as nickel. 

The invention of US-A-4989067 relates to interconnections from an HgCdTe detector chip to a silicon read-out chip. A beam lead interconnect formed on a silicon chip is used to provide connections with a finer pitch than is achievable when wire-bonding is used. 

This figure shows the conductor pattern 3 overlapping exposed parts of the electrode leads 13 and fanning out on the substrate 20 to form wider terminal areas for wire-bonding. Common connections 6 and 26 are provided. 

Metal conductors are necessary for applying electrical potentials to the silicon structures. Due to the small size and the material a direct welding or wire bonding... 

After the DRIE-process the second glass wafer is bonded on top of the silicon structures to close the plasma and the ionization chamber. It also serves to mechanically stabilize the system. To install the electrical contacts and the gas supply the PIMMS chip is glued to a PCB and the gold pads of the chip are connected via wire bonding to the PCB. After that, as described in Sect. 4, capillaries are glued to the plasma-/ionization-chamber inlet to connect the PIMMS to plasma and sample gas supplies. 

A 48 x 48 active-matrix OLED display was completed on flexible PET substrates. The completed display is shown bent, after wire bonding, in Fig. 15.22. Figure 15.23 shows the display brightness under different data voltages, and Fig. 15.24 demonstrates its flexible functionality during operation. Despite the many noticeable defects on the display, which are expected for displays fabricated outside a dean room, the display was characterized by good drive performance and uniformity. 

Fig. 15.22. A 48 x 48 OTFT-driven OLED display on PET, shown after wire bonding.

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