Conductor pattern

Additive Approach. In the additive approach (Figure 18), a negative image of the conductor pattern is defined in a photoresist layer that must be thicker than the conductor layer. Metal is then selectively deposited in the open areas of the resist by electroplating or by a lift-off technique. For... 

Deposit conductor Pattern photoresist Etch conductor vias and lines... 

A variety of etching processes are available for conductor patterning. 

This figure shows the conductor pattern 3 overlapping exposed parts of the electrode leads 13 and fanning out on the substrate 20 to form wider terminal areas for wire-bonding. Common connections 6 and 26 are provided. 

Figure 2.11. Scanning electron micrograph of an active device after defining the conductor pattern. The extent of the topography is evident. Courtesy of...

The copper foil is subsequently covered with a photoresist layer that is patterned by lithography techniques to produce the desired circuitry. Areas of exposed, cross-linked resist protect the copper that is to remain on the board as circuitry. The unprotected copper that is not needed for the circuitry is etched away, usually with ferric chloride solution. At this point, the printed board must have the following characteristics the substrate has to be structurally sound (no delamination), and the copper conductor patterns have to adhere well to the substrate in addition, the assembly should have good dimensional stability, and it has to show good solderability (ability to withstand short exposures to liquid solder at temperatures around 250 C or higher) to allow for the connection of components and devices to the circuitry. 

In the IC industry electroless metal deposition can be used for contact filling, via filling, and conductor patterns. In micromachining electroless deposition can be used for all of the same purposes but also to make structural microelements from a wide variety of metals, metal alloys, and even composite materials. 

The roots of circuit boards stretch all the way back to 1925, when Ducas was granted a patent for a method of forming electroplated conductor patterns in copper, gold, or silver on a nonconductive base material. Although he formed the conductor patterns by stenciling rather than photoetching, these patterns are of interest because of their remarkable resemblance to modern-day circuit patterns. He stenciled a conductive paste on a plastic base and electroplated it with the aforementioned metals. 

FIGURE 6 Two packaging approaches for hybrid GaAs/Si smart pixels, (a) Both chips flip-chip bonded side-by-side on a transparent substrate with interchip electrical connections provided by metal conductors patterned on the substrate, (b) One chip flip-chip bonded to the other, followed by substrate removal. 

---