D Integration

Face-to-face Bonding Face-to-back Bonding 

Intuitively, many advantages can be expected through the adoption of 2.5-D integration scheme. A few of these are discussed below. 

CAD tools to find a more efficient packing of circuits according to their inherent topology. Thus, a systematic reduction in the on-chip wire length can be expected, which can be translated into speed gain, power saving, and many other advantages. 

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Tadepalli R, Thompson CV. Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits. Proceedings of The IEEE International Interconnect Technology Conference 2003. p 36-38. 

In Chapter 2, we present a unified cost analysis among five different integration schemes monolithic System-on-Chip, Multiple-Reticle-Wafer, Multi-Chip Module, 2.5-D integration, and 3-D integration. Our results proved that the 2.5-D integration scheme could be the most cost efficient under a group of reasonable assumptions. 

K. W. Guarini, et al.. Electrical integrity of state-of-the-art 0.13 mm SOI CMOS devices and circuits transferred for three-dimensional (3-D) integrated circuit (IC) fabrication. In Proc. IntT Electronic Device Meeting, 2002, pp. 943 - 945. 

Ziptronix Inc.. 3-D integration, [online]. Available http //www.ziptronix.com/. 

Abstract Besides the dominant monolithic VLSI integration paradigm, many non-monolithic schemes have already been developed in the past. Typical such schemes include wafer scale integration or multi-reticle wafer, multi-chip module, and 3-D integration. In this chapter we compared these different schemes in a unified cost analysis framework. Our model takes a few parameters extracted from representative fabrication and evaluates the cost efficiency. Our analysis proves that the proposed 2.5-D out significantly outperform other integration paradigms from a cost perspective. 

Keywords 2.5-D integration, monolithic VLSI integration, multi-reticle wafer, multi-chip module, 3-D integration, yield, silicon area, fault coverage. 

D ICs can be dated back to as early as 1980s (e.g., [7,8]) and has been followed by many recent developments. Fabrication technologies for the 3-D integration can be classified into two categories silicon re-growth and wafer bonding. 

Table 2.1 Wafer bonding based 3-D integration technologies...

Within the paradigm of 3-D integration, the input VLSI system is built into m device layers, each having an equal area of A/m. The yield of the 3-D implementation is the accumulative yield over all layers ... 

While the yield loss has to accumulate in the fabrication process, the Y 1 factor in the denominator suggests that the 3-D integration scheme is inherently more costly than the monolithic scheme. As a matter of fact, when the 3-D bonding step has an assembling yield of 95%, the total consumed silicon area of the 3-D implementation is 28.1 cm. ... 

Under the 2.5/3-D integration context, the floorplanning problem can be formulated with different flavors according to the architecture of the designed system. Here we can classify VLSI system into three categories ... 

Besides traditional optimization objectives, a 3-D VLSI system implies a larger power density than its monolithic equivalent does. On-chip hot spots could incur serious degradations of system performance, power consumption, and reliability. However, we do observe that a 2.5/3-D floorplan without thermal constraints could lead to a maximum temperature of 180°C and a temperature gradient of 152°C[11] with traditional air-cooling techniques. Accordingly, it s of key importance to avoid excessive heat build-up and temperature difference in a 3-D integrated system. In other words, the thermal objective must be taken into account in the 3-D floorplanning problems formulated above. 

Abstract This chapter covers the placement solutions for 2.5-D/3-D integrated circuits. Based on a partition technique, our placement techniques could handle VLSI circuits consisting of both standard cells and macros. The detailed result analysis justifies the potential of the 2.5-D integration approach to improve system performance and lower interconnect power consumption. 

To the best of my knowledge, this book is the first one to give a complete overview of the 3-D integration problem. It would provide valuable information for readers from various communities, such as semiconductor fabrication process developers, IC designers, and EDA R D practitioners. The book could also serve as an excellent reference for graduates majoring in microelectronics. 

Insofar as the concept of elecbode is concerned, it is important to stress here that most electrodes for elecbochemical application in alternative energy devices are manufactured mainly by interfacing semiconducting nanosbuctures with conducting substrates. By combining different elecbodes, one can attain a three-dimensional (3-D) integrated elecbochemical cell [85-87]. Elecbodes can... 

Baum M, Jia C, Haubold M, Wiemer M, Schneider A, Rank H, Trautmann A, Gessner T (2010) Eutectic wafer bonding for 3-D integration. 3rd electronics system integration technology conference (ESTC), Berlin... 

Hosur, M.V., Abdullah, M., and Jeelani, S. (2005) Manufacturing and low-velocity impact characterization of foam filled 3-D integrated core sandwich composites with hybrid face sheets. Composite Structures, 69, 167-181. 

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