Interconnection Technology

Connectors and Interconnection Handbook, 5 vols.. International Institute of Connector and Interconnection Technology, Inc., Anaheim, Calif. emphasis on electronic connector design. 

F. N. Sinnadurai, Handbook of Microelectronics Packaging and Interconnection Technologies, Electrochemical Pubhcations Limited, 1985, p. 8. 

Anaya, N., et al., Copper Interconnection Technology for Silicon Large Scale Integrated Circuits,""NTTR D, 45(4) 373-8 (1996)... 

It may be considered a fortunate coincidence that this book is published at the time of the introduction of copper interconnection technology in the microelectronics industry. In 1998 the major electronic manufacturers of integrated circuits (ICs) are switching from aluminum conductors produced by physical methods (evaporation) to copper conductors manufactured by electrochemical methods (electrodeposition). This revolutionary change from physical to electrochemical techniques in the production of microconductors on silicon is bound to generate an increased interest and an urgent need for familiarity with the fundamentals of electrochemical deposition. This book should be of great help in this crucial time. 

The acceptance of chemical mechanical planarization (CMP) as a manufacturable process for state-of-the-art interconnect technology has made it possible to rely on CMP technology for numerous semiconductor manufacturing process applications. These applications include shallow trench isolation (STI), deep trench capacitors, local tungsten interconnects, inter-level-dielectric (ILD) planarization, and copper damascene. In this chapter. 

D. Ouma, D. Boning, J. Chung, G. Shinn, L. Olsen, and J. Clark, An Integrated Characterization and Modeling Methodology for CMP Dielectric Planarization, International Interconnect Technology Conference, San Francisco, CA, June 1998. 

F. G. Shi, B. Zhao, S.-Q. Wang, A New Theory for CMP with Soft Pads, Proceedings of International Interconnect Technology Conference, San Francisco, CA, pp. 73-75, June 1998. 

K. Sato, S. Harada, A. Saiki, T. Kimura, T. Okubo and K. Mukai, A novel planar multilevel interconnection technology utilizing polyimide, IEEE Trans. Parts,... 

K. Mukai, A. Saiki, K. Yamanaka, S. Harada and S. Shoji, Planar multilevel interconnection technology employing a polyimide, IEEE J. Solid-State Circuits, SC-13 (4), pp 462-467, Aug. 1978. 

These characteristics show that perfluorinated polyimides are promising materials for waveguides in integrated optics and optical interconnect technology. The thermal, mechanical, and optical properties of perfluorinated polyimides can be controlled by copolymerization in the same manner as partially fluorinated polyimides. ... 

With the increase of the degree of integration of microcircuits, the multilevel interconnect technology becomes inevitable for future VLSI manufacture. Polyimide exhibits superior planarity over stepped structures and is expected to be one of the most promising materials for the dielectric insulation of VLSI s. However, since the smallest via holes so far achieved by wet etching is 3 pm (1), the formation of fine via holes by a dry etch process is needed for the application of polyimide to VLSI having fine metal wiring. 

Schwartz GC, Srikrishnan KV, Gross A, editors. Handbook of Semiconductor Interconnection Technology. Marcel Dekker 1997. p 287. 

Rahman A, Fan A, Chung J, Reif R. Wire-length distribution of three-dimensional integrated circuits. IEEE International Interconnect Technology Conference 1999.p 233-235. 

Bamal M, List S, Stucci M, Verhulst A, M VanHove, Cartuyvels R, Beyer G, Maex K. Performance comparison of interconnect technology and architecture options... 

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