Floorplanning for 2.5-D Integration

Institute of Microelectronics, Tsinghua University Beijing 100084, P. R. China, dengyd tsinghua.edu.cn 

Electrical and Computer Engineering Carnegie Mellon University 5000 Forbes Avenue, Pittsburgh, PA 15213-3891 USA, maly ece.cmu.edu 

Keywords 2.5-D integration, floorplanning, bounded-slice line, simulated annealing, temperature distribution, thermal-driven. 

In the previous chapter, we briefly outlined our 2.5-D layout synthesis framework. In this chapter, the 2.5-D layout tools are applied on floorplan level designs. We will introduce our floorplanning algorithms along with the design case studies in this chapter. 

Under the 2.5/3-D integration context, the floorplanning problem can be formulated with different flavors according to the architecture of the designed system. Here we can classify VLSI system into three categories  

---

A Series of 2.5-D Physical Design Tools Due to the complexity of modem ASIC designs, automatic EDA tools are critical for a successful layout implementation. For 2.5-D integrated ASIC systems, additional complexity is introduced by the large amount of inter-chip communication resource. To be able to pack an ASIC system in a 2.5-D space, we developed 2.5-D floorplanning, placement and... 

---