Testing Techniques for 2.5-D Integration

In the first chapter, we briefly reviewed the potential techniques to solve the testing problem for 2.5-D integrated systems. Based on various isolation and selftesting methodologies, these testing solutions could well handle the block-based design style in which every functional block is located within a specific chip and the inter-chip interconnections are only assigned to inter-block wires. 

We believe that 2.5-D DFT techniques should be developed to resolve the above problems. The test data compression technique would be essential to test a partial netlist with a large number of inter-chip contacts based I/O. Extra testing circuitry should be inserted so that compressed test results can be accessed through conventional testing pads (e.g., on the boundary) of a chip. Meanwhile, scan chains 

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