Placement for 2.5-D Integration

Institute of Microelectronics, Tsinghua University Beijing 100084, P. R. China, dengyd tsinghua.edu.cn 

Electrical and Computer Engineering Carnegie Mellon University 5000 Forbes Avenue, Pittsburgh, PA 15213-3891 USA, maly ece.cmu.edu 

Abstract This chapter covers the placement solutions for 2.5-D/3-D integrated circuits. Based on a partition technique, our placement techniques could handle VLSI circuits consisting of both standard cells and macros. The detailed result analysis justifies the potential of the 2.5-D integration approach to improve system performance and lower interconnect power consumption. 

Keywords 2.5-D integration, placement, partition, mixed layout, standard cell, macro, wire length, inter-chip contact. 

As we have proved the potential of the 2.5-D integration scheme at the floorplan level in the last chapter, it s appealing to investigate the feasibility at the 

---

A Series of 2.5-D Physical Design Tools Due to the complexity of modem ASIC designs, automatic EDA tools are critical for a successful layout implementation. For 2.5-D integrated ASIC systems, additional complexity is introduced by the large amount of inter-chip communication resource. To be able to pack an ASIC system in a 2.5-D space, we developed 2.5-D floorplanning, placement and... 

The layout style using mixed macro/standard cells is proper for VLSI design containing IP blocks and embedded memories to be aggressively optimized in a flattened manner. In this layout style, a small number of large macros are scattered in a sea of standard cells. For this layout style, a natural question is whether the cell area variability will impair the efficiency of 2.5-D integration. Therefore, we enhance our placement framework with capabilities of handling macros. 

---