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Multiple-Reticle Wafer

In Chapter 2, we present a unified cost analysis among five different integration schemes monolithic System-on-Chip, Multiple-Reticle-Wafer, Multi-Chip Module, 2.5-D integration, and 3-D integration. Our results proved that the 2.5-D integration scheme could be the most cost efficient under a group of reasonable assumptions. [Pg.14]

Figure 2.1 Total consumed silicon area of multiple-reticle wafer... Figure 2.1 Total consumed silicon area of multiple-reticle wafer...
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Multiple-Reticle Wafer (MRW)

Total consumed silicon area of multiple-reticle wafer

Wafers

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