Tungsten interconnects

Since 1987 several papers have described the incorporation of blanket tungsten CVD for interconnect applications. 

Kaanta et al.142 implemented tungsten for contact fill, via studs, and the first interconnect metal. The via plug was produced by the blanket etch back method. The apparent disadvantage of the higher resistivity of tungsten as the interconnect was compensated by  

Chapman et al.143 used W as the metal 1 material, they filled the vias using a selective tungsten process. 

A 2 urn pitch triple-level metal process using two levels of tungsten interconnect was reported by Bonifield et al.144. The third metal level was still Al-Cu(2%) driven by the requirements of wire bonding. For the vias between metal 2 and metal 3 a selective tungsten process was used. 

Planarization of the tungsten lines was accomplished using the REB technique. 

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The acceptance of chemical mechanical planarization (CMP) as a manufacturable process for state-of-the-art interconnect technology has made it possible to rely on CMP technology for numerous semiconductor manufacturing process applications. These applications include shallow trench isolation (STI), deep trench capacitors, local tungsten interconnects, inter-level-dielectric (ILD) planarization, and copper damascene. In this chapter. 

In cases where tungsten interconnect is possible, blanket tungsten will remain the most attractive technology. The only replacement for this... 

Tungsten silicide gates interconnections of cold wall 1 Torr... 

Interconnect. Three-dimensional structures require interconnections between the various levels. This is achieved by small, high aspect-ratio holes that provide electrical contact. These holes include the contact fills which connect the semiconductor silicon area of the device to the first-level metal, and the via holes which connect the first level metal to the second and subsequent metal levels (see Fig. 13.1). The interconnect presents a major fabrication challenge since these high-aspect holes, which may be as small as 0.25 im across, must be completely filled with a diffusion barrier material (such as CVD titanium nitride) and a conductor metal such as CVD tungsten. The ability to fill the interconnects is a major factor in selecting a thin-film deposition process. 

The interconnecting holes are narrow and deep (at times less than 0.25 im wide and up to 2 im or more in depth) and, after a diffusion-barrier layer is applied, it must be filled completely with a high-conductivity metal (usually aluminum or tungsten) to provide the low-resi stance plug for inter-layer connections. Typically, CVD provides better step coverage and conformity than sputtering and other physical-vapor deposition processes. 

A typical example of the complexity of interconnection assembly consists of a MOCVD-TiN diffusion barrier combined with a low-temperature (260°C) CVD aluminum with low resistivity (<3 lQ-cm). A copper doping forms an overlying sputtered Al-Cu film. This aluminum plug provides a large reduction in resistance compared to the classical tungsten process. k" ... 

Tungsten for Interconnections. CVD tungsten is now replacing sputtered aluminum for the filling of interconnection holes with the following advantages 1 11 1... 

Damacene (Al,Cu) or copper interconnects Tungsten plugs - n Type silicon... 

A number of works have focused on the pattern dependencies in tungsten (both tungsten via and local interconnect) polishing [12,19,21]. To first order, empirical results seem to suggest that dishing is dominated by the width or size of the metal feature being polished wide lines tend to suffer... 

Shih, Y.-C., Sethuraman, A., Wang, H.-M., Lavoie, R., Cook, L. (1997). Polishing pads and process effects on tungsten CMP. Proc. 2nd Int. CMP for ULSI Multilevel Interconnect. Conf, Santa Clara, pp. 237-240. 

In reflectometry, the light passes through the films to be measured. Beneath the transparent films, there must be an opaque substrate through which light does not pass. The substrate characteristics must be modeled correctly to calculate the thicknesses of the films above. In silicon processing, theoretically, any of the commonly used metal materials, such as the titanium nitride (TiN), aluminum (Al), and tungsten (W), can be used as substrates. However, in reality, whereas a PMD oxide can be measured on the polysilicon material used in poly interconnections, an ILD oxide can not be measured directly on TiN, because the TiN layer used is too thin to be opaque. TiN is semitransparent if its thickness is less than 1000 A. A thin... 

Framework (skeleton) structures of oxides have been identified for fast ion conduction of Na" and other ions (Goodenough et al., 1976). One-, two- or three-dimensional space is interconnected by large bottlenecks in these oxide hosts. While the tungsten bronze and j8-alumina structures contain one- and two-dimensional interstitial space, the hexagonal framework of NaZr2(P04)3 has a three-dimensional... 

Chemical Vapor Deposition. Deposition of tungsten, molybdenum, and their silicides by chemical yapor deposition (CVD) is of relatively recent interest in the microelectronics industry. These materials arc useful for gates and interconnects in metal oxide semiconductors (MOS) devices. Aluminum, the widely used interconnect material, has a comparatively low melting point (600°C) and a markedly different coefficient of thermal expansion (compared to silicon), so that over a period of years researchers have been seeking an alternative for aluminum,... 

In the fabrication of semiconductors, CVD is an important technique for the thin-film formations with an increase in device intensity performance. Tungsten hexafluoride has been widely used as a source gas of tungsten silicide (WSi,v) and tungsten metal for electrodes and interconnects. 

Ramarajan S, Li Y, Hariharaputhiran M, Babu SV, Her YS. The role of alumina particle density in chemical mechanical planarization of copper, tantalum, and tungsten disks and films. J CMP On-Chip Interconnect IMIC 2000 l(l) 28-38. 

Tungsten CMP, to a lesser extent, has also been utilized to construct tungsten lines as a part of the interconnect via damascene or dual-damascene... 

FIGURE 9.4 A cross section of a typical testing wafer in which tungsten lines are used as an interconnect (from Ref. 13). 

Similar to copper and STI CMP, tungsten CMP constructs vias and sometimes lines as a part of the interconnect in IC fabrication. The ability to form these microstructures enables the multilevel interconnect network that shortens the... 

Two challenges are uniform thinning of the top wafer and high aspect ratio etching of the thinned layer. An approach to high-density TSV interconnection using a variety of CMOS-compatible fabrication steps (such as CVD tungsten and polysilicon, BCD copper, and solder micro-bumps) is presented by Knickerbocker et al. in References 86 and 87. 

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