Shallow-trench isolation

L(XIOS isolation introduces nonplanarity, and a bird s beak at the edge of the active region reduces the packing density of the circuitry, both of which make LOCOS undesirable at sub-0.5 pm dimensions. As a result, new isolation schemes are being intro- 

CMOS devices are very sensitive to damage to the silicon substrate. Therefore care must be taken to ensure that the oxide CMP process used for STT has low defect densities and stops on the Si3N4 mask layer. Li particular scratches must be kept to a minimum. Also, because the oxide CMP processes tend to have low selectivity to Si3N4, the amount of overpolishing performed must be kept to a minimum, which requires high polish rate uniformity to ensure that all of the SiOj overburden is cleared evenly. 

As explained above, the basic advantage of STI over LOCOS is the improved control of the former over the geometry of the isolation area. Here, a standard process flow for manufacturing STI with direct planarization is presented. The important considerations for each step are mentioned along with typical process and geometry parameters. Additional process steps required for various optimization techniques are added to this process flow depending on the specific technique. These steps are described in Section 12.4. 

FIGURE 12.3 Schematic cross sections showing the major STI fabrication steps. 

FIGURE 12.4 Schematic cross section of a wafer with block resist-RIE for non-CMP planarization before (above) and after RIE (below). 

CMP comes next. Its goal is to planarize and pattern the oxide [14]. The CMP step is discussed in more detail in the following two chapters. It should be mentioned here that CMP is not the only option for planarization. More cost-effective solutions have been studied and used, such as multilayer resist processes and spin-on glass in combination with RIE (Fig. 12.4). However, the obtained global planarity for such non-CMP processes is inferior to CMP planarity. They are therefore more suitable for ILD planarization than for STI 

Looking at the process steps that are responsible for the geometry of the active and isolation areas, it is easy to see the extent to which STI scalability 

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Application(s) Si stock polish tungsten damascene CMP Si final polish CMP post-CMP buff Si stock ILD CMP metal dual damascene ILD CMP shallow trench Isolation metal dual damascene... 

MOSFETT s, and silicon oxide is deposited. The source/drain positions where electrical contact is to be made to the MOSFETs are defined, using the oxide-removal mask and an etch process. For shallow trench isolation, anisotropic silicon etch, thermal oxidation, oxide fill and chemical mechanical leveling are the processes employed. For shallow source/drains formation, ion implantation techniques are still be used. For raised source/drains (as shown in the above diagram) cobalt silicide is being used instead of Ti/TLN silicides. Cobalt metal is deposited and reacted by a rapid thermal treatment to form the silicide. Capacitors were made in 1997 from various oxides and nitrides. The use of tantalmn pentoxide in 1999 has proven superior. Platinum is used as the plate material. 

The acceptance of chemical mechanical planarization (CMP) as a manufacturable process for state-of-the-art interconnect technology has made it possible to rely on CMP technology for numerous semiconductor manufacturing process applications. These applications include shallow trench isolation (STI), deep trench capacitors, local tungsten interconnects, inter-level-dielectric (ILD) planarization, and copper damascene. In this chapter. 

Y.-L. Wang, C. Liu, M.-S. Feng, J. Dun, K.-S. Chou, Effects of underlying films on the chemical-mechanical polishing for shallow trench isolation technology, J. Thin Solid Films, 308 309, pp. 543-549, 1997. 

B. Withers, E. Zhoa, R. Jairath, A Wide Margin CMP and Clean Process for Shallow Trench Isolation Applications, 1998 Proceedings of the Third International Chemical-Mechanical Planarization for VLSI Multilevel Interconnection Conference (CMP-MIC), Santa Clara, CA, pp. 319-327, Feb. 19-20,1998. 

Fig. 5. Pattern dependent issues in oxide planarization and polishing of shallow trench isolation and metal damascene structures.

Fig. 18. Model fit for nitride phase of shallow trench isolation polish [31].

A key benefit of accurate CMP models that needs emphasis is the capability to optimize layout design before polishing. Post-CMP ILD thickness variation is a serious concern from both functionality and reliability concerns. An effective method of minimizing this effect is the use of dummy fill patterns that lead to a more equitable pattern density distribution across the chip. Evaluation of such schemes before actual product implementation has become a major use of CMP modeling [53]. Dummy fill is also being investigated for front-end processes where shallow trench isolation CMP suffers from substantial pattern dependencies. 

J. T. Pan, D. Ouma, P. Li, D. Boning, F. Redecker, J. Chung, and J. Whitby, Planarization and Integration of Shallow Trench Isolation, VLSI Multilevel Interconnect Conference, Santa Clara, CA, June 1998. 

Today s CMP applications concern both front-end steps such as shallow trench isolation (STI) and inter metal dielectric (IMD) in the back end of the line. 

Another important microstructure in IC manufacturing process is shallow trench isolation (STI) that allows the effective separation of active devices and increase of packing densities. Figure 1.23 shows a schematic of an STI structure before and after polishing [51]. It is important for the dishing of the oxide in the trench and the nitride loss to be as low as possible. 

Schlueter J. Trench warfare CMP and shallow trench isolation. Semiconductor International October 1999. 

Bu K-H, Moudgil BM. Colloidal silica based high selectivity shallow trench isolation (STI) chemical mechanical polishing (CMP) slurry. Proceedings of MRS. Symposium W. Spring 2005. 

SHALLOW TRENCH ISOLATION CHEMICAL MECHANICAL PLANARIZATION... 

Before discussing shallow trench isolation, a brief summary should be made about its predecessor—the local oxidation of silicon [7]—as an illustration of... 

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