Chip interconnect

A current example of a problem that can be simplified through segregation of its components by physical scale is the deposition of on-chip interconnects onto a wafer. Takahashi and Gross have analyzed the scaling properties of interconnect fabrication problems and identified the relevant control parameters for the different levels of pattern scale [135], They define several dimensionless groups which determine the type of problem that must be solved at each level. 

Multichip Packaging. A solution to these problems is to mount a number of ICs closely together on a common substrate within an MCP. The obvious advantages of the MCP are the reduction in the overall size and weight of the package and, thus, the reduction in the size and cost of the system. The reliability of the system is also improved, because the chip-to-chip interconnections can be accomplished within the package, which reduces the number of package-to-board connections. 

For electrically short interconnections with high resistance, such as on-chip interconnections, signal delays are dominated by the rise time degradation due to the charging of the receiver capacitance by the interconnection resistance (fllineCrec) (54, 55). On PWBs in which resistance is negligible, the... 

Kaufman F et al. Chemical-mechanical polishing for fabricating patterned W metal features as chip interconnects. J Electrochem Soc 1991 138 (11) 3460- 3465. 

Ramarajan S, Li Y, Hariharaputhiran M, Babu SV, Her YS. The role of alumina particle density in chemical mechanical planarization of copper, tantalum, and tungsten disks and films. J CMP On-Chip Interconnect IMIC 2000 l(l) 28-38. 

Thermal expansion coefficient and mismatch between expansion coefficients of package and chip interconnect. 

P.C. Andriacacos, Copper on-chip interconnections. Electrochem. Soc. Interface 8, 32-37, 1999. 

The multiscale systems approach is directly applicable to problems in nanotechnology, molecular nanotechnology and molecular manufacturing. The key ideas have been illustrated with examples from two processes of importance to the semiconductor industry the electrodeposition of copper to form on-chip interconnects and junction formation in metal oxide semiconductor field effect transistors. 

Andricacos, P.C. (1999) Copper on-Chip Interconnections - A Breakthrough in Electrodeposition to Make Better Chips. 

Andricacos PC (1999) Copper on-chip interconnections a breakthrough in electrodeposition to make better chips. Electrochem Soc Interface 8 32-37... 

Edelstein DC et al (1995) VLSI on-chip interconnection performance simulations and measurements. IBM J Res Dev 39 383 02... 

Ordered polymer films made from poly benzthiazole (PBZT) and poly benzoxazole (PBO) can be used as substrates for multilayer printed circuit boards and advanced interconnects to fill the current need for high speed, high density packaging. Foster-Miller, Inc. has made thin substrates (0.002 in.) using biaxially oriented liquid crystal polymer films processed from nematic solutions. PBZT films were processed and laminated to make a substrate with dielectric constant of 2.8 at 1 MHz, and a controllable CTE of 3 to 7 ppm/°C. The films were evaluated for use in multilayer boards (MLBs) which require thin interconnect substrates with uniform controllable coefficient of thermal expansion (CTE), excellent dielectric properties, low moisture absorption, high temperature capability, and simple reliable processing methods. We found that ordered polymer films surpass the limitations of fiber reinforced resins and meet the requirements of future chip-to-chip interconnection. 

Parasitics are an important factor in the decision for monolithic integration versus two-chip solutions. Owing to their small dimensions, the practically achievable sense capacitance in many surface micromachined devices with typical 2 pm gaps and film thickness is often 100 fF or less. Since chip-to-chip interconnections, even using solder bumps, add at least 1 pF parasitic capacitance, on-chip electronics is usually required to achieve the highest possible sensitivity. Bulk-mi-cromachined devices have much higher sense capacitance in this case a two-chip solution may not incur a resolution penalty. 

Stacking more layers of DRAMs on the top For instance, when 3 layers of DRAM dies are stacked on the top of the microprocessor die, 576 MB is available, which is applicable for most applications. A 5-layer DRAM could suffice high-end applications. The major concern of such a configuration is heat dissipation. Fortunately, DRAM usually has relatively low power consumption. If there s still excessive heat build-up, hardware based heat dissipation techniques like heat pipes (e.g., dummy inter-chip interconnects) have to be installed. 

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