Step coverage

A critical issue is the step coverage of the adhesion layer. This should be sufficient such that both the adhesion and the (chemical) barrier properties of the film are maintained. The minimum required step coverage depends upon the allowed nominal thickness at the top oxide surface (see figure 2.2) and the minimum thickness where both adhesion and the barrier properties of the material are still present. Assuming that for safety reasons a minimum thickness of the order of 0.05 pm is needed and that the nominal thickness will be of the order of 0.1 pm, then the step coverage should be 50%. For sputtered TiW in a contact of a radius of one micron and an aspect ratio of one, 50% step coverage has been shown to be achievable [Eltwanger et al.7]. 

Problems, however, are expected when the radius becomes smaller 

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Dielectric Film Deposition. Dielectric films are found in all VLSI circuits to provide insulation between conducting layers, as diffusion and ion implantation (qv) masks, for diffusion from doped oxides, to cap doped films to prevent outdiffusion, and for passivating devices as a measure of protection against external contamination, moisture, and scratches. Properties that define the nature and function of dielectric films are the dielectric constant, the process temperature, and specific fabrication characteristics such as step coverage, gap-filling capabihties, density stress, contamination, thickness uniformity, deposition rate, and moisture resistance (2). Several processes are used to deposit dielectric films including atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), or plasma-enhanced CVD (PECVD) (see Plasma technology). 

Historically, SOG techniques have been used the most for IMD fabrication, but TEOS/o2one (TEOS/O ) processes are more recent developments that have been increasing in popularity based on excellent step coverage and void-free characteristics. TEOS/O doped with boron and phosphoms (BPTEOS/O ) has replaced BPSG in small-scale devices, and has been used successfully in 4- and 16-Mb DRAM production (16). 

Aluminum, the most common material used for contacts, is easy to use, has low resistivity, and reduces surface Si02 to form interfacial metal-oxide bonds that promote adhesion to the substrate. However, as designs reach submicrometer dimensions, aluminum, Al, has been found to be a poor choice for metallization of contacts and via holes. Al has relatively poor step coverage, which is nonuniform layer thickness when deposited over right-angled geometric features. This leads to keyhole void formation when spaces between features are smaller than 0.7 p.m. New collimated sputtering techniques can extend the lower limit of Al use to 0.5-p.m appHcations. 

Etch Profiles. The final profile of a wet etch can be strongly influenced by the crystalline orientation of the semiconductor sample. Many wet etches have different etch rates for various exposed crystal planes. In contrast, several etches are available for specific materials which show Httle dependence on the crystal plane, resulting in a nearly perfect isotropic profile. The different profiles that can be achieved in GaAs etching, as well as InP-based materials, have been discussed (130—132). Similar behavior can be expected for other crystalline semiconductors. It can be important to control the etch profile if a subsequent metallisation step has to pass over the etched step. For reflable metal step coverage it is desirable to have a sloped etched step or at worst a vertical profile. If the profile is re-entrant (concave) then it is possible to have a break in the metal film, causing an open defect. 

As shown in Ch. 2, the effect of pressure on the nature of the deposit is considerable. At high pressure (i.e., ca. atmospheric), the deposition is diffusion limited and, at low pressure, surface reaction is the determining factor. In practical terms, this means that low pressure generally provides deposits with greater uniformity, better step coverage, and improved quality. 

Deposition of TiN by the thermal decomposition of tetrakis(dimethylamido)titanium (TDMAT) in a nitrogen atmosphere (as opposed to ammonia) was characterized by a simple Arrhenius rate expression. Adequate deposition rates and good step coverage were achieved for 3/1 aspect ratio holes, 0.40 micron in size. A reactor model was designed,... 

The interconnecting holes are narrow and deep (at times less than 0.25 im wide and up to 2 im or more in depth) and, after a diffusion-barrier layer is applied, it must be filled completely with a high-conductivity metal (usually aluminum or tungsten) to provide the low-resi stance plug for inter-layer connections. Typically, CVD provides better step coverage and conformity than sputtering and other physical-vapor deposition processes. 

In devices with geometry below the 0.25 im level, titanium nitride will likely replace titanium-tungsten, since it has better barrier properties. The process of choice will likely be CVD, which offers improved uniformity and step coverage, although improvements in collimated sputtering may keep that process on line for a while. 

Ternary Nitrides as Diffusion Barriers. Barrier layers with good step coverage and low resistivity are formed from ternary nitrides with various compositions Ti-Si-N, W-Si-N, and W-B-N. They are deposited by MOCVD with deposition temperatures between 300 and 450°C. Complete step coverage is obtained on reentrant features as low as 0.25 micron with an aspect ratio of 4.0.Pi]... 

Chemical Vapor Deposition- Deposition of silicon oxide films is accomplished by CVD equipment. Either plasma CVD or ozone oxidation is used. Blanket tungsten films are also deposited by CVD equipment to create contact and via plugs. Polysilicon and silicon nitride films are deposited in hot-wall furnaces. TiN diffusion barrier films are deposited by either sputtering or CVD, the latter giving superior step coverage. 

Advantages 1) Low Temperature 2) Controllable Composition 3) Step Coverage 4) Pinhole Free 5) Fast Deposition Rates 6) Can Produce Graded Interfaces... 

Spray 2nm-20pm Fast and adaptable to complex shapes and sizes, conformal step coverage, high efficiency Expensive, low- viscosity coating solution Electrical insulation, circuit board housing... 

This last constraint is imposed so that the grain size and other temperature-dependent material properties of the grown film and also its step coverage do not show excessive variations. 

On the other hand, if uniform step coverage is desired, a tapered profile like that in Figure 14 is essential since highly anisotropic profiles... 

The properties of silicon dioxide films also depend upon all plasma deposition parameters. Temperature is the critical parameter (240), although the compressive stress level varies with rf frequency (237, 240). Film topography can be varied during deposition by altering ion bombardment conditions (242, 243). In particular, the incorporation of Ar in the deposition atmosphere enhances sputtering and thus promotes conformal step coverage during film formation (243). 

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