Etched back

Several contending technologies are presently being used to achieve local and global planarizations that include spin on deposition (SOD), reflow of boron phosphorous silicate glass (BPSG), spin etch planarization (SEP), reactive ion etching and etch back (RIE EB), spin on deposition and etch back... 

Another established optimization technique is patterned oxide etch back [14]. Its purpose is to remove most of the oxide in active areas prior to CMP. An additional lithography step is performed in order to mask the isolation areas... 

FIGURE 12.17 Schematic cross section of a wafer with reverse oxide etch back after lithography (above) and before CMP (below). 

FIGURE 12.18 AFM scan (above) and cross section across the dashed line (below) of a transistor area on a wafer with oxide etch back after planarization and nitride strip. 

Neureither B, Binder F, Fischer E, Gabric Z, Koller K, Rohl S. Resist etch back as a manufacturable low cost alternative to CMP.Proceedings of the Eleventh International VLSI Multilevel Interconnect Conference 1994. pl51-157. 

A second method of local planarization involves spinning photoresist onto the SiOj ILD to obtain local planarity. The resist is then hard baked and etched with an RIE etch tailored to remove SiOz (or ILD) at the same rate as the photoresist. Because the etch rate of the two materials is equal, the planarity of the resist film transfers into the SiOz film. However, a precise match in SiOj and photoresist etch rates is difficult to maintain because the relative ratio of SiOj to photoresist exposed increases as the etch back proceeds. Loading effects then result in a decrease in the Si02 etch rate and increase in the photoresist etch rate. Furthermore, polymer deposits build up on the etch reactor chamber walls over time etching of this polymer depletes the chemicals used to etch the photoresist, which slows the photoresist etch rate. If the etch rates are not matched, the planarity of the photoresist layer will not transfer well to the SiOz. 

Lastly, if the SiOj deposition is highly conformal, the regions between closely spaced metal lines may be filled without the production of gaps. If the film thickness is equal to half the space width, the space will fill completely and the comers of the film will join at the top of the space, thereby leaving a nearly planar film. Examples of CVD SiOj processes capable of the required high degree of conformality are ECR deposition and tetraethyl orthosilicate (TEOS) plasma CVD-enhanced. While this approach yields local planarization above closely spaced lines, the wide spaces between metal lines are not filled, and thus a sharp step is experienced at the edge of such spaces. Therefore, this approach is often coupled with SOG or resist etch-back processes or CMP.< >... 

Figure 5.35 Junction leakage between CMP and resist etch back (REB) planarized wafers with either silicon or TiSij contacts. (S = silicon, T = TiSij, C = CMP, and R = REB.) (From Ref. (25).)...

In addition, several issues arise with the use of either RIE etch back or CMP to remove the metal from on top of ILD. Dual layw inlaid metal schemes have been demonstrated for tungsten, aluminum, copper,and gold metallization systems. 

As with oxide CMP (Chapter 5), metal CMP may enhance yields by virtue of reduced defect densities. In addition to a reduction in nonplanarity induced defects (Section 5.24), CMP is a cleaner process than the relatively dirty RIE etch back processes. Figure 6.5 shows a 3X reduction in particles using CMP vs. RIE. The result is a decrease in metal-to-metal shorts on the subsequent interconnection level (Figure 6.6). As with oxide CMP, increased die yields is one of the major driving forces for acceptance of metal CMP processes for tungsten stud formation. ... 

RE etch back or CMP may be used to remove the polysilicon overburden. When RE etch back is used, however, a center seam is etched into the trench. In addition, the RE etch is not self-arresting, and therefore leads to a step at the oxide-polysilicon edge. These defects reduce planarity and make it difficult to reliably cover the trench with the strap film. Center seam and edge step defects in deep trench formation are analogous to the same defects that form when RE etch back is used to remove the... 

Unlike W plasma etch back process, the typical W CMP process usually removes the adhesion layer such as Ti/TiN or TiN during the primary polish. As a result, during the over polish step there is some oxide loss. Since the oxide deposition, planarization CMP (oxide CMP), and tungsten CMP steps are subsequent to each other, the oxide thickness profile could become worse further into the process flow. Therefore, the across-wafer non-uniformity of the oxide loss during W CMP process is one of the very important process parameters needs to be optimized. To determine the effect of the process and hardware parameters on the polish rate and the across-wafer uniformity, designed experiments were run and trends were determined using analysis of variance techniques. Table speed, wafer carrier speed, down force, back pressure, blocked hole pattern, and carrier types were examined for their effects on polish rate and across-wafer uniformity. The variable ranges encompassed by the experiments used in this study are summarized in Table I. 

The partially oxidized sihcon species are responsible for the anodic current transient measured at the end of etching of an anodic oxide film-covered n-Si electrode in the dark as shown in Fig. 3.25. For a clean n-Si surface, the anodic current is very small. This dark current during the etch-back experiment, whose peak position depends on the thickness, occurs on anodic oxide as well as on thermal oxide. The data shown in Fig. 3.25 indicate that the anodic reaction proceeds by injection of electrons from the partially oxidized sihcon species at the sihcon/oxide interface. The amount of charge associated with the current transient, which is similar for anodically and thermally oxidized surface, is about 4.4 x 10 C/cm corresponding to two monolayers of on a (100) surface. The partially oxidized species may extend to a number of atomic layers, fewer for thermal oxide than anodic oxide as shown in Fig. 3.25. 

FIGURE 3.25. Anodic current transient measured on anodic oxide and thermal oxide during etch-back in a HF solution. (Reprinted from Matsumura and Morrison. " 1983, with permission from Elsevier Science.)... 

M. Tajima, S. Ibuka, H. Aga, and T. Abe, Characterization of bond and etch-back silicon-on-insulator wafers by photoluminescence under ultraviolet excitation, Appl. Phys. Lett. 70(2), 231, 1997. 

---