Planarization, in integrated circuit

Chemical Mechanical Planarization in Integrated Circuit Manufacturing... 

Before the invention of the planar transistor, many photoresist processes were developed for the manufacture of circuit boards. Experience gained in this area was rapidly transferred to silicon processing, and much of the early work in integrated circuit lithography can be traced directly to circuit board manufacturing. 

The increasing importance of multilevel interconnection systems and surface passivation in integrated circuit fabrication has stimulated interest in polyimide films for application in silicon device processing both as multilevel insulators and overcoat layers. The ability of polyimide films to planarize stepped device geometries, as well as their thermal and chemical inertness have been previously reported, as have various physical and electrical parameters related to circuit stability and reliability in use (1, 3). This paper focuses on three aspects of the electrical conductivity of polyimide (PI) films prepared from Hitachi and DuPont resins, indicating implications of each conductivity component for device reliability. The three forms of polyimide conductivity considered here are bulk electronic ionic, associated with intentional sodium contamination and surface or interface conductance. 

Thin films (qv) of vitreous silica have been used extensively in semiconductor technology. These serve as insulating layers between conductor stripes and a semiconductor surface in integrated circuits, and as a surface passivation material in planar diodes, transistors, and injection lasers. They are also used for diffusion masking, as etchant surfaces, and for encapsulation and protection of completed electronic devices. Thin films serve an important function in multilayer conductor insulation technology where a variety of conducting paths are deposited in overlay patterns and insulating layers are required for separation. 

Prior to the introduction of Cu electroplating, the primary method used to form a multilevel structure of interconnections in integrated circuit applications was A1 and Al-alloy metallization.49 Localized porous-type anodization was developed in the 1970s to obtain planar interconnection metallization for multilevel large-scale integration (LSI) 26,46,50 For example, Schwartz and Platter showed that the subtractive etching for A1 interconnects could be substituted... 

Procedures for thermal oxidation of SiC have been developed and shown to produce oxide layers useful in the fabrication of planar SiC microelectronic devices. The SiC oxidation rate has been studied under conditions commonly used in integrated circuit fabrication. The oxidation rate constants derived in these studies are useful for predicting the oxide thickness formed on SiC under similar conditions. The metal-oxide-semiconductor capacitors formed by thermal oxide layers on both 3C- and 6H-SiC have been shown to have low interface charge densities, suitable for transistor applications. 

Luo, J. and Dorfeld, D. A., Material Removal Regions in Chemical Mechanical Planarization for Sub-micron Integrated Circuit Fabrication Coupling Effects of Slurry Chemicals, Abrasive Size Distribution and Wafer-Pad Contact Area, IEEE Trans. Semicond. Manuf, Vol. 16, No. 1, 2003, pp. 45-56. 

To understand the impact of a CMP process on a certain product with a unique integrated circuit pattern, it is desirable to measure areas with different feature sizes and shapes. Since CMP polish rate may be affected by pattern density, areas encompassing various features should be included in the measurement program. The within-die thickness nonuniformity will indicate the planarization capability of a CMP process. 

As the integrated circuit (IC) industry has chosen chemical mechanical planarization (CMP) as one of the indispensable processes in the generations of transistor gate lengths equal to or smaller than 0.35/im, it is imperative that the CMP-related process problems be investigated and... 

Polyimides, both photodefinable and nonphotodefinable, are coming into increased use. Applications include planarizing interlayer dielectrics on integrated circuits and for interconnects, passivation layers, thermal and mechanical stress buffers in packaging, alpha particle barriers on memory devices, and ion implantation (qv) and dry etching masks. 

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