Device geometry

Figure 11.18 Manufacturing scale-up device for microchan-nel FT. The device geometry is 0.6 m x 0.6 m x 0.15 m and contains more than 10 000 coolant and process channels.

Erley G, Gorer S, Penner RM (1998) Transient photocurrent spectroscopy Electrical detection of optical absorption for supported semiconductor nanocrystals in a simple device geometry. Appl Phys Lett 72 2301-2303... 

Figure 21. Device geometry (a) and model system (b) used for the calculation of the I V) characteristics. (Reprinted with permission from Ref [50], 2005, American Physical Society.)...

Erosion is typically characterized by either occurring on the surface or in the bulk. Surface erosion is controlled by the chemical reaction and/or dissolution kinetics, while bulk erosion is controlled by diffusion and transport processes such as polymer swelling, diffusion of water through the polymer matrix, and the diffusion of degradation products from the swollen polymer matrix. The processes of surface and bulk erosion are compared schematically in Fig. 1. These two processes are idealized descriptions. In real systems, the tendency towards surface versus bulk erosion behavior is a function of the particular chemistry and device geometry (Tamada and Langer, 1993). Surface erosion may permit the... 

For good aspect ratio and device geometry, anisotropic etching agents have to exhibit a strong difference in etch rate between crystal directions. In a typical KOH solution for single crystal Si, about a two orders of magnitude smaller etch rate in... 

We have shown that antiresonant dielectric layers can be used to design low-loss liquid-core waveguides that are suitable for implementing planar sensor device geometries. The following sections will describe in more detail how the design principles laid out here were implemented in silicon-based LC-ARROW chips and used for optical sensing and detection of a wide variety of substances. 

Finally, as device geometries decrease, spacings between stripes of resist also decrease. With micron and submicron patterns, the surface tension of etch solutions can cause the liquid to bridge the space between two resist stripes. Etching of the underlying film is thereby precluded. 

While the metal (primarily Fe, iron) contamination of W CMP does not directly lead to any functionality or yield loss in the manufacturing of products of the current 0.35- m or larger technologies, it is questionable that the Fe contamination can be acceptable for the products with device geometries 0.25 fim and smaller. As the speed of the transistor increases to a certain crossover point, the speed of the integrated circuit as a whole becomes predominately dictated by the back-end processes [21]. 

The increasing importance of multilevel interconnection systems and surface passivation in integrated circuit fabrication has stimulated interest in polyimide films for application in silicon device processing both as multilevel insulators and overcoat layers. The ability of polyimide films to planarize stepped device geometries, as well as their thermal and chemical inertness have been previously reported, as have various physical and electrical parameters related to circuit stability and reliability in use (1, 3). This paper focuses on three aspects of the electrical conductivity of polyimide (PI) films prepared from Hitachi and DuPont resins, indicating implications of each conductivity component for device reliability. The three forms of polyimide conductivity considered here are bulk electronic ionic, associated with intentional sodium contamination and surface or interface conductance. 

The read-out structure is further improved in EP-A-0061801 where each strip comprises a recess extending across a part of the width of the strip from the opposite side of the strip and towards a protruding connection. The protruding connection at one side of one strip extends into the recess at the opposite side of an adjacent strip. In this way a compact device geometry is achieved. 

As device geometries become smaller and smaller, the epi layers also scale down and become thinner. The thinner the epi layer, the more serious the autodoping problem becomes. Very sharp transitions are needed, and cannot be ob tained readily at normal temperatures (>1000°C). Therefore, there is great interest in finding a low-temperature epi process that produces good quality epi layers. 

Fig. 10.1. Schematic illustrations of two device geometries for organic thin-film transistors. Part (a) shows the layout of a top contact device in which the source and drain electrodes are deposited on top of the...

This chapter summarizes some of our recent work in printing techniques and plastic electronics. It also presents new data from printed transistors that use several different organic semiconductors in a variety of device geometries. In all cases, we observed good performance. pCP for the source/drain electrodes is attractive because it provides a simple and potentially low-cost route to high resolution (i.e. small channel lengths, L) structures that can be used to build transistors which... 

Because the select TFT is used only for (dis)charging the storage capacitor (the gate capacitor of the drive TFT is much smaller than the storage capacitor), we can use a small device geometry, W = 20 pm, L = 20 pm. This transistor is basically working in the linear region, and the on-resistance of the select TFT can be calculated by use of Eq. (2) ... 

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