Tri-gate transistors

Tri-gate transistor architechture with high-k gate dielectrics metal gates and strain engineering. Digest of Technical Papers, IEEE Trans VLSI Tech Symp 62... 

FIGURE 20.10 Intel Corp. s schematic representation of a tri-gate transistor and an SEM image of a seven-leg tri-gate transistor. The use of three dimensions allows aerial scaling while increasing the width of transistor channel used for conduction (from Ref. 8). 

Figure 4.17. SEM image of a nonplanar tri-gate transistors. Also shown is the enhanced electron flow (shown in red) of (a) tri-gate, relative to (b) standard planar MOSFETs. Reproduced with permission from Intel Corporation (http //www.intel.com).

The most thoroughly studied double-gate MOSFET is known as the FinFET (Hisamoto et al., 1998 Kedzierski et al., 2001 Yu et al., 2002) and in slightly modified forms as the tri-gate transistor (Doyle et al., 2003) or omega-FET... 

Doyle, B., B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, R. Chau. 2003. Tri-gate fully-depleted cmos transistors fabrication, design and layout. Symposium on VLSI Technology, Digest of Technical Papers 133-134. 

As a first demonstration of the fabrication of TFT devices by digital lithography, tri-layer insulated-gate thin-film transistors were fabricated on four-inch glass substrates using a three-layer wax-mask process. Mask layers were used to define the... 

Fig. 8.9. (a) Schematic cross section of the device structure (not to scale) showing the gate electrode integrated into the microfluidic channel, (b) Typical I-V characteristics measured with 10 mM Tris-Cl buffer solution flowing across the PEDOT PSS transistor at 0.1 pi min-1. Reprinted with permission from [33]. Copyright 2005 American Institute of Physics... 

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