Dielectric intermetal

Another important use of dielectrics is as intermetal dielectrics (IMDs), where the dielectrics insulate metal lines from each other. The dielectric material must fill small gaps with high aspect ratios (depth to width) while maintaining all other dielectric properties. It is essential that the IMDs are void-free at submicrometer dimensions for both performance and rehabiUty. 

Step 11. If no additional metallisa tion layers are required, the substrate is covered with a passivation layer. If additional levels of metallisa tion are to be added to the stmcture, a blanket layer of a intermetal dielectric (IMD) is deposited. The resist is deposited, patterned (mask 5), and vias down to the Al in the first metal layer are etched. Steps 10 and 11 are repeated to form the second metal layer. 

Fig. 9. Fabrication sequence for an oxide-isolated -weU CMOS process, where is boron and X is arsenic. See text, (a) Formation of blanket pod oxide and Si N layer resist patterning (mask 1) ion implantation of channel stoppers (chanstop) (steps 1—3). (b) Growth of isolation field oxide removal of resist, Si N, and pod oxide growth of thin (<200 nm) Si02 gate oxide layer (steps 4—6). (c) Deposition and patterning of polysihcon gate formation of -source and drain (steps 7,8). (d) Deposition of thick Si02 blanket layer etch to form contact windows down to source, drain, and gate (step 9). (e) Metallisation of contact windows with W blanket deposition of Al patterning of metal (steps 10,11). The deposition of intermetal dielectric or final...

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

Integration of Cu with a dielectric introduces new problems and challenges [1(b), 34-36] (Fig. 19.8). For example, if polyimides are used as intermetal dielectrics, reliability concerns are corrosion of underlying metal and adhesion of metal films to polyimide underlayers [1(b)]. 

Silicon Dioxide. Si02 layers produced by PECVD are useful for intermetal dielectric layers and mechanical or chemical protection and as diffusion masks and gate oxides on compound-semiconductor devices. The films are generally formed by the plasma-enhanced reaction of SiH4 at 200-300 °C with nitrous oxide (N20), but CO, C02, or 02 have also been used (238-241). Other silicon sources including tetramethoxysilane, methyl dimethoxysilane, and tetramethylsilane have also been investigated (202). Diborane or phosphine can be added to the deposition atmosphere to form doped oxide layers. 

Layers Typical materials for which CMP processes originally have been developed for microelectronic applications include various types of silicon dioxide such as thermal oxide, TEOS, HDP, BPSG, and other B- or P-doped oxide films. These films are used for various isolation purposes including interlevel dielectric (ILD), intermetal dielectric (IMD), or shallow trench isolation (STI). In addition, n- or p-doped poly-Si, which is a semiconducting material used as capacitor electrode material for DRAMS or gate electrode for MOS applications (CMOS as well as power MOS devices), also has to be polished. Metals for which CMP processes have emerged over the last 10-15 years are W for vertical interconnects (vias) and most importantly Cu as a low-resistivity replacement for aluminum interconnects, employed in the damascene or dual-damascene processing scheme. Other metals that are required for future nonvolatile memories are noble metals like Pt or Ir for which CMP processes have been explored. 

Organosilicon polymers are becoming important in many aspects of device technology. Multilevel metallization schemes require the use of a thin dielectric barrier between successive metal layers (i). Often, these dielectric materials are silicon oxides that are deposited by low-temperature or plasma-enhanced chemical vapor deposition (CVD) techniques. Although conformal in nature, CVD films used as intermetal dielectrics frequently result in defects that arise fi om the high aspect ratios of the metal lines and other device topographies (2). Several planarization schemes have been proposed to alleviate these problems, some of which involve the use of organosilicon polymers (2-4). 

Dielectric CMP is used to planarize intermetal dielectrics (IMD) (represented by ILDl, ILD2, or ILD3) and premetal dielectrics (represented by ILDO). The slurry typically used in this process is at high pH (10-12), KOH or NH4OH based and silica abrasive. The hydroxide ion is needed to hydrolyze the substrate, which in this case is Si02-... 

In recent years, the IR absorption of fluorinated silicon oxide (FjcSiOj,) has been actively studied [68-74]. These films are very easily deposited by several PECVD or liquid-phase deposition (LPD) methods and are characterized by a low dielectric constant, which decreases with increased concentration of fluorine in the film. Decreasing the dielectric constant of the intermetal dielectric film is the most efficient way to reduce the adjacent wiring capacitance, which will improve the performance of submicrometer integrated circuits. However, the F SiOy films become reactive to water as the fluorine concentration increases. The film desorbs H2O and HF under thermal annealing after humidification, which causes reliability problems in the VLSI fabrication [68]. 

Some requirements to use these polymers for interlayer and intermetal dielectrics in advanced microelectronic applications are high thermal stability, high glass transition temperature, good mechanical properties, low dielectric constant, low coefficient of thermal expansion and low moisture absorption. The dielectric constant of polyimides depends mainly on the... 

Intermetal Dielectric (IMD) - Insulating films used between adjacent metal lines typically silicon dioxide. 

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