Multilevel metallization

Polysilicon. Polysihcon is used as the gate electrode material in MOS devices, as a conducting material for multilevel metallization, and as contact material for devices having shallow junctions. It is prepared by pyrolyzing silane, SiH, at 575—650°C in a low pressure reactor. The temperature of the process affects the properties of the final film. Higher process temperatures increase the deposition rate, but degrade the uniformity of the layer. Lower temperatures may improve the uniformity, but reduce the throughput to an impractical level. 

HANDBOOKOF MULTILEVEL METALLIZATION FOR INTEGRATED CIRCUITS edited by Syd R. Wilson, Clarence J. Tracy, and Jchn L. Freeman, Jr. 

There is a basic difference between the damascene and through-mask plating processes in the way the trenches and vias are filled with electrochemically deposited Cu, through either an eiectrodeposition or an electroless technique. In multilevel metal structures, vias provide a path for connecting two conductive regions separated... 

Oxidation of Silicon. Silicon dioxide [7631-86-9], Si02, is a basic component of IC fabrication. Si02 layers are commonly used as selective masks against the implantation or diffusion of dopants into silicon. Si02 is also used to isolate one device from another. It is a component of MOS devices, and provides electrical isolation of multilevel metallization structures (12). A comparison of Si and Si02 properties is shown in Table 1. 

Turley, A.P. and Herman, D.S., LSI Yield Projections Based Upon Test Pattern Results An Application to Multilevel metal Structures . IEEE Trans, on Parts, Hybrids, and Packaging, Volume PHP-10, no. 4, pp. 230-234, December (1974). 

Freeman JL, Tracy CJ, Wilson SR, editors. Handbook of Multilevel Metallization for Integrated Circuits Materials, Technology, and Applications. Noyes Publications 1993. p 352. 

Contolini RJ, Bernhardt AF, Mayer ST. Electrochemical planarization for multilevel metallization. J Electrochem Soc 1994 141 2503-2510. 

Treichel H, Frausto R, Srivastan S, Whithers B. Process optimization of dielectrics chemical-mechanical planarization processes for ultralarge scale integration multilevel metallization. J Vac Sci Technol A 1999 17.4 1160-1167. 

Organosilicon polymers are becoming important in many aspects of device technology. Multilevel metallization schemes require the use of a thin dielectric barrier between successive metal layers (i). Often, these dielectric materials are silicon oxides that are deposited by low-temperature or plasma-enhanced chemical vapor deposition (CVD) techniques. Although conformal in nature, CVD films used as intermetal dielectrics frequently result in defects that arise fi om the high aspect ratios of the metal lines and other device topographies (2). Several planarization schemes have been proposed to alleviate these problems, some of which involve the use of organosilicon polymers (2-4). 

J. Olsen and F. Moghadam, Planarization Techniques, in Multilevel Metallization for Integrated Circuits, eds. S.R. Wilson, C.J. Tracy, and J.L. Freeman, Noyes Publications, Park Ridge, NJ (1993). 

In addition to the multilevel metallization and formation of interconnects, anodic processing of A1 was employed for the fabrication of integrated passive components thin film capacitors and inductors.56,57 For example, localized porous-type anodization of A1 films was used to convert 20- am-thick A1 to the dielectric layer of porous AI2O3 and to define metal-dielectric-metal structures.56 The... 

One of the challenges in multilevel metallization of the sub-0.5 pm generation devices is the void-free filling of high aspect ratio (depth-to-width ratio) contact holes at low temperatures [73, 80]. These holes connect one level of metal with another level of metal above or below (see Fig. 3-4). It is possible to connect the first level of metal with the gate, source and drain of the transistor. Non-conformal films can cause shoulders at the top of the contact or keyhole void formation by closing the holes. 

Figure 5-4. A schematic drawing of a multilevel metallization structure made possible by planarization.

The processes of planarization is vital for the development of multilevel structures in VLSI circuits. To minimize interconnection resistance and conserve chip area, multilevel metallization schemes are being developed in which the interconnects run in three dimensions. Figure 5-4 shows a schematic of the multilevel metallization made possible by planarization. 

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