Dual damascene processes

Figure 19.3. Process steps for the dual damascene process (a) deposition of dielectric b) dielectric RIE to define via and line (c) deposition of diffusion barrier and Cu seed iayer (d) eiectrodeposition of Cu into via and trenches foiiowed by Cu CMP.

Layers Typical materials for which CMP processes originally have been developed for microelectronic applications include various types of silicon dioxide such as thermal oxide, TEOS, HDP, BPSG, and other B- or P-doped oxide films. These films are used for various isolation purposes including interlevel dielectric (ILD), intermetal dielectric (IMD), or shallow trench isolation (STI). In addition, n- or p-doped poly-Si, which is a semiconducting material used as capacitor electrode material for DRAMS or gate electrode for MOS applications (CMOS as well as power MOS devices), also has to be polished. Metals for which CMP processes have emerged over the last 10-15 years are W for vertical interconnects (vias) and most importantly Cu as a low-resistivity replacement for aluminum interconnects, employed in the damascene or dual-damascene processing scheme. Other metals that are required for future nonvolatile memories are noble metals like Pt or Ir for which CMP processes have been explored. 

The name damascene derives from a technique of making inlaid metals that originated in ancient Damascus, now in present day Syria. See, for example, P. Singer, Making the move to dual damascene processing, Semiconductor Int, pp. 70 82 (Jan. 1999). 

The ideal deposition process would leave a perfectly flat surface. That does not happen, so a planarization process is required to maintain depth of field requirements. For a dielectric planarization process, the ideal planarization process would remove only material in the up areas and remove no material in the down areas. Metal CMP involves the removal of metal overburden, leaving filled plugs or vias (single damascene) or filled vias and inlaid metal lines (dual damascene) with no removal of metal in the inlaid region and no removal of dielectric. 

Aruanchalam V, Smith G, Kailasam S, Knorr A, Hettiaratchi K, Rozbicki R, Pfeifer K, Ho P, Pyun J. Comparison of barrier-first and argon pre-clean first processes for copper metallization in ultra low-k (ULK) dual damascene integration. Proceedings of the Advanced Metallization Conference 2005 p 413-419. 

Figure 16.19 Process steps for dual damascene copper interconnect formation (a) ILD oxide (Si02) deposition by means of PECVD (b) silicon nitride (SiN) deposition...

Finally, the excess copper is polished away by means of CMP. This process step planarizes the surface and prepares it for the next level. The dual damascene technique can be repeated as many times as necessary, until the required number of copper metal layers are formed. 

C.K. Chang, T.H. Foo, M. Murkhetjee-Roy, V.N. Bliznetov, H.Y. Li, Enhancing the efficiency of postetch polymer removal using megasonic wet clean for 0.13-pm dual damascene interconnect process. Thin Solid Films 462 (2004) 292. 

In addition, some resists have been developed for special applications and with special properties. This is the case for example in microelectronics, where special hybrid organic-inorganic materials with low dielectric constants and high thermal and mechanical stability are being developed to simplify the dual damascene electrical interconnection process [56]. Also, resists loaded with functional nanoparticles can be patterned using NIL [57]. 

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