Interlevel dielectric

Dielectrics for Interlevel Wiring and Planarization. When connecting a number of devices to form a circuit it is often necessary to cross wires without actual electrical contact between them. In order to accomplish this multiple levels of wiring separated by dielectric films are necessary. 

Passivation layers, multilayer resist stacks, diffusion barriers, interlevel dielectrics, side-wall spacers, trench masks, oxidation masks, etc., in semiconductor devices. 

Currently, there is a trend of low dielectric constant (low-k) interlevel dielectrics materials to replace Si02 for better mechanical character, thermal stability, and thermal conductivity [37,63,64]. The lower the k value is, the softer the material is, and therefore, there will be a big difference between the elastic modulus of metal and that of the low-k material. The dehiscence between the surfaces of copper and low-k material, the deformation and the rupture of copper wire will take place during CMP as shown in Fig. 28 [65]. 

Pattern dependency concerns arise at two levels in STI CMP [67] during the oxide overburden polish phase, and when the nitride layer is exposed. In the first stage, the process is similar to interlevel dielectric (ILD) CMP and the characterization and modeling methodologies presented in the previous section are applicable. Once the nitride is exposed, two different materials exist at the same level, and pattern dependency manifestation is more complex. 

The function of the interlevel dielectric of the multilevel structure is three-fold (1) it must provide planarization of underlying topography while allowing high resolution patterning of via holes necessary for contact between metal layers, (2) it must provide insulation integrity, and (3) it must contribute minimally to device capacitance. 

A likely candidate for the role of interlevel dielectric is polyimide on the basis of its relative purity and planarizing spin-on application. In fact, planarizing metal with polymer or so-called PMP technology was pioneered by Hitachi to develop two metal level transistors. More recently, several other... 

The present work is a report of the properties of polyimide which define functionality as an interlevel dielectric/passivant. Thus, the planarizing and patterning characteristics and electrical characteristics of current vs voltage, dissipation, breakdown field strength, dielectric constant, charge and crossover isolation are discussed in addition to the reliability-related passivation properties. 

The breakdown field strength is a thickness dependent property, a probable reflection of pinhole density variation with thickness. For a typical value of Interlevel dielectric film thickness (1 - 2 p), the breakdown field strength is 1 - 2.5 x 10 V/cm which is adequate for most applications. 

The electrical properties of the polylmldes Investigated are all consistent with good Interlevel dielectric performance. The room temperature I-V characteristic Indicates non-llnearlty of current density with field or square root of field. At typical field use conditions of 5 x 10 V/cm, polylmlde conductivity Is A-10 which Is similar to that of thermal SIO2. At higher fields such as 2 x 10 V/cm, conductivity of polylmlde Increases... 

The type of adhesion dealt with in the examples in the second paragraph above and Fig. 1 is mechanical or structural while for the lithographic resist adhesion requirements described in this paper a more practical definition of adhesion, one first proposed by Mittal [16], is being referenced and used. Resist patterning layer-substrate adhesion is required only to process or pattern a particular device layer. After the circuit layer is patterned, the resist layer is removed and does not become an integral part of the circuit, as opposed to a PI interlevel metal dielectric layer which does. As such, it is not required to possess high mechanical adhesion strength. In fact, the resist layer must be quantitatively removed after the circuit required layer has been patterned. If the resist layer adheres too well and becomes difficult to remove, it actually interferes with successful circuit fabrication. 

Silicon Nitride. Silicon nitride produced by high-temperature (>700 °C) CVD is a dense, stable, adherent dielectric that is useful as a passivation or protective coating, interlevel metal dielectric layer, and antireflection coating in solar cells and photodetectors. However, these applications often demand low deposition temperatures (<400 °C) so that low-melting-point substrates or films (e.g., Al or polymers) can be coated. Therefore, considerable effort has been expended to form high-quality silicon nitride films by PECVD. 

In the case of a photoresist, the ultimate definable feature size together with the ability of the material to withstand either chemical etchants or plasma environments determines the domain of utility. The feature size is in turn determined by the wavelength required for exposure, the sensitivity and contrast of the resist, and the dimensional stability of the material during exposure, development, and subsequent processing. Adhesion of the resist to the substrate is critical both for patterning and use, and adhesion can be affected by surface preparations, and by residual stresses developed during deposition and cure. While photo-imagable polyimides have been introduced, their principal intended application is as a component of the finished part, either as passivant or interlevel dielectric (see below). 

In order for a polyimide to be useful as an interlevel dielectric or protective overcoat (passivant), additional demanding property requirements must be met In the case of the passivant, the material must be an excellent electrical insulator, must adhere well to the substrate, and must provide a barrier for transport of chemical species that could attack the underlying device. It has been demonstrated that polyimide filrns can be excellent bulk barriers to contaminant ion motion (such as sodium) [10], but polyimides do absorb moisture [11,12], and if the absorbed moisture affects adhesion to the substrate, then reliability problems can result at sites where adhesion fails. However, in the absence of adhesion failure, the bulk electrical resistance of the polyimide at ordinary device operating temperatures and voltages appears to be high enough to prevent electrochemical corrosion [13]. 

When used as an interlevel dielectric, even greater demands are placed on the polyimide. Because integrated circuit processing includes as a final step a metal sinter at 400 C, the interlevel insulator film must withstand such exposures without degradation of electrical, chemical, or mechanical properties. In addition, the deposition, cure, and etch process must provide for reliable interconnection between the metal layers above and beneath the film (the "via contact") [8]. Issues of ion motion, moisture uptake, and electrical conduction both in bulk and at interfaces must also be considered carefully. 

Layers Typical materials for which CMP processes originally have been developed for microelectronic applications include various types of silicon dioxide such as thermal oxide, TEOS, HDP, BPSG, and other B- or P-doped oxide films. These films are used for various isolation purposes including interlevel dielectric (ILD), intermetal dielectric (IMD), or shallow trench isolation (STI). In addition, n- or p-doped poly-Si, which is a semiconducting material used as capacitor electrode material for DRAMS or gate electrode for MOS applications (CMOS as well as power MOS devices), also has to be polished. Metals for which CMP processes have emerged over the last 10-15 years are W for vertical interconnects (vias) and most importantly Cu as a low-resistivity replacement for aluminum interconnects, employed in the damascene or dual-damascene processing scheme. Other metals that are required for future nonvolatile memories are noble metals like Pt or Ir for which CMP processes have been explored. 

Jeong Y, Kim SY, Seo YJ. System facility factors for hot spot reduction of interlevel dielectric (ILD) CMP process. Proc ISEIM 2001 p 95. 

Bath SH, Legegett R, Maury A, Monning K, Tolies R. Planarizing interlevel dielectrics by chemical mechanical polishing. Solid State Technol 1992 35 p 87. 

Recently CMP of an interlevel dielectric SiO, deposited using evaporation techniques, was carried out for superconducting circuits. "CMP of the interlevel dielectric film allows the junction area to be greatly reduced, thereby increasing the speeds of operation of the circuits, by eliminating the need to open vias to make contact to the top electrode. ITie key to the success was in (a) the precise control to terminate the CMP within 200 nm after reaching the endpoint and (b) the ability to planarize a few hundred-micron-wide features. 

In previous work, we have formalized the notions of planarization length and planarization response function as key parameters that characterize a given CMP consumable set and process. Once extracted through experiments using carefully designed characterization mask sets, these parameters can be used to predict polish performance in CMP for arbitrary product layouts. The methodology has proven effective at predicting oxide interlevel dielectric planarization results. 

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