High-level synthesis

Traditionally, synthesis has been subdivided into the following main categories  

An integrated synthesis system that covers all three synthesis levels is often referred to as a silicon compiler. In a sense, it represents the ultimate synthesis tool and the major challenge in synthesis. Such a tool would allow the design of electronic circuits from a high-level, behavioral specification with little or no human intervention. 

High-level synthesis has been an active area of research for over 20 years. The main problems involved, such as scheduling, allocation and module assignment, have been well characterized and solved. Nevertheless, high-level synthesis systems are not yet common on the marketplace. We see four principal reasons for this. 

The third reason has been the lack of a generally accepted synthesis-oriented HDL in the past. Such an HDL must serve as the common input for synthesis as well as simulation, test generation, etc. 

This book presents a detailed survey of existing high-level synthesis systems. Naturally, academic approaches are in the majority, but surprisingly many industrial research systems could be included. The book begins with an introduction to high-level synthesis, which covers both design representation and the sequence of steps 

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Edery, I., Altmann, M., and Sonenberg, N. (1988). High-level synthesis in Escherichia coli of functional cap-binding eukaryotic initiation factor eIF-4E and affinity purification using a simplified cap-analog resin. Gene 74, 517-525. 

High-Level Synthesis and Secretion of a-Amylase from Rice Callus... 

Baneijea, A. C., Brechling, K. A., Ray, C. A., Erikson, H., Pickup, D. J., andjoklik, W. K. (1988). High-level synthesis of biologically active reovirus protein crl in a mammalian expression vector system. Virology 167, 601-612. 

The misincorporation of norleucine for methionine was known to occur in bacteria when high level synthesis of recombinant proteins were induced in minimal medium fermentation (1,2). This misincorporation was detected in the production of N-labeled recombinant human leptin produced using minimal medium conditions, however, is not present in the clinical samples produced using other fermentation conditions. The mechanism for the misincorporation was believed to involve the de novo synthesized norleucine which bypasses the leucine biosynthetic pathway and enters directly into the... 

Deng, T., Noel, J. P., and Tsai, M.-D. (1990). A novel expression vector for high-level synthesis and secretion of foreign proteins in Escherichia coli Overproduction of bovine pancreatic phospholipase A2. Gene 93, 229-234. 

Keywords Electronic Nose System, Principal Component Analysis, Decision Tree, High Level Synthesis, Vivado, Zynq System on Chip... 

Ait Si Ah, A., Amira, A., Bensaali, F., Benanunar, M., Hardware PCA for gas identification systems using high level synthesis on the Zynq SoC. In Electronics, Circuits, and Systems (ICECS), IEEE 20th International Conference on December 2013, 707-710,2013. 

Hardware compilation, high-level synthesis, automated hardware synthesis, attribute grammars, formal synthesis methods, attribute grammar evaluators... 

All these proUems motivated tiie search for formal methods to describe and perform high-level synthesis. One of the first proposals (Hofer, 1983), int er linear programming, is still considered as a widely used methoddqgy (Lin, 1997). However, its computational complexity limits its q>[dication to very small problems. 

Design entry in a high-level synthesis system is an algorithmic description written in a common programming language (like PASCAL or FORTRAN), or by a special purpose hardware description language (HIX), such as ISPS, DSL or VHDL. 

Once the CDFG has been constructed, the three central synthesis tasks in a typical high-level synthesis system are the following ... 

As stated above, the first step in high-level synthesis is the c( iq lation of the input specification to a dataflow type internal representation. This step has many similarities with dataflow CQnq)uting, for which, an AG formalism has been given... 

G. Economakos received his Diploma in Electrical and Canq>uter Engineering from the National Technical Uiiversity of Athens (1992). Currently, he is a Fh.D. student in the National Technicfd Chiversity of Athens. Hs research interests include hardware design automation, combinational synthesis, sequential synthesis, high-level synthesis and language based design automation. 

Automatic Post-Synthesis Verification Support for a High Level Synthesis Step by using the HOL Theorem Proving System... 

Formal hardware verification, high level synthesis, theorem proving... 

We here discuss the development of post-synthesis verification support for a high level synthesis step, which translates a data flow description to a register transfer description (Gajski, Dutt, Wu Lin 1992, Camposano Wolf 1991). Additional information provided by the high level synthesis tools consists of scheduling and allocation results. For the verification support the hardware models are defined, the correctness lemma is proved, and the verification procedure is developed. The practicability of our approach has been turned out by working with three concrete scenarios (the same verification support is used in all three scenarios) ... 

While these are applications of the high level synthesis verification support, we here focus on the development of this support. ... 

High level synthesis results are often assumed to be correct by construction. In (Ugurdag Fuhrman 1996) it is mentioned that an industry designer can never rely on such an assumption. At least validation or better verification with respect to executable models derived from hardware description... 

So, the first pre-synthesis veriflcation step was to formulate a requirement, which arise from the high level synthesis paradigm. Assuming this requirement allows to make the mutually recursive equations defining register values more similar to the single recursive equation defining the value of the data flow variables. For a concrete synthesis result, we have to check that the requirement in fact is satisfied (post-synthesis work). 

We now have a collection of conditions, which are sufficient for correctness of a high level synthesis result. The conditions directly are motivated from the high level synthesis paradigm. This result was proved for the parameterized models and therefore holds for each concrete synthesis result. Therefore, we only need to prove for each concrete synthesis result, that the conditions hold for the concrete synthesis result. This is the post-synthesis task. 

We are also working on synthesis steps following the high level synthesis step presented here. The timing of register transfer level descriptions is based on a control step scheme, and there are several alternatives to implement a control step scheme by clocking schemes. We will apply formal synthesis methods to map control step based descriptions to clock cycle based descriptions. 

Eisenbiegler, D., Blumenrohr, C. Kumar, R. (1996), Implementation issues about the embedding of existing high level synthesis algorithms in HOL, in Proc. TPHOL 96 , Turku (Finland), pp. 157-172. 

Gajski, D., Dutt, N., Wu, A. k Lin, S. (1992), High-level synthesis introduction to chip and system design, Kluwer Academic Publishers. 

In order to provide complete support for the high-level synthesis trajectory, many design problems must be addressed. We do not claim that the material presented in this book covers the complete path, and certainly not all target application domains or architecture styles. However, we do believe we have contributed to the solution of a number of the most crucial problems in the domains of architecture synthesis and the related issue of behavioral specification. 

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