Silicon compiler

D. Gajski, editor. Silicon Compilation. Addison-Wesley, 1988. 

J. Rabaey, H. De Man, J. Vanhoof, G. Goossens, and F. Catthoor. CATHEDRAL II a synthesis system for multi-processor DSP systems. In D. Gajski, editor, Silicon Compilation, pages 311-360. Addison-Wesley, 1988. 

P. Lippens, J. van Meerbergen, A. van der Werf, W. Verhaegh, B. Mc-Sweeney, J. Huisken, and 0. McArdle. PHIDEO a silicon compiler for high speed algorithms. Proc. 2nd ACM/IEEE Europ. Design Automation Conf., Amsterdam, The Netherlands, pages 436-441, Feb 1991. 

Although behavioral silicon compilation has made large strides toward the automation of VLSI design [3, 9], the use of such systems is currently very limited in industrial environments. The main problems are ... 

R. Jamier and A. A. Jerraya. APOLLON a data-path silicon compiler. IEEE Circuits Devices May 1985. 

Misha R. Burich. Design of module generators and silicon compilers. In D. Gajski, editor, Silicon Compilation Addison-Wesley, 1988. 

G. De Micheli. Synthesis of control systems. In G. De Micheli, A. Sangiovanni-Vincentelli, and P. Antognetti, editors, Design systems for VLSI Circuits Logic Synthesis and Silicon Compilation Martinus Nijhoff, pages 327-364, 1987. 

K. Ranerup. Proving functional correctness of control unit layout in silicon compilation environments. Technical report. Esprit project BRA 3281, LU/m30/El/4. 

HIGH-LEVEL SYNTHESIS FOR REAL-TIME DIGITAL SIGNAL PROCESSING The Cathedral-II Silicon Compiler, J. Vanhoof, K. van Rompaey, I. Bolsens, G. Gossens, H. DeMan ISBN 0-7923-9313-9... 

Silicon compilers, synthesis tools Software programs that can construct an ASIC whose functionality is no longer described by a circuit schematic but in a special high level computer languages, generally called hardware description languages or HDL. 

The task of selecting the systems to include in the survey was by no means an easy one. There is a fairly strong consensus today on exactly what the term liigh-level synthesis means, and only the systems that fit this definition were included. However, any restriction by topic always raises border cases. For this survey, systems that convert Register-Transfer level descriptions into logic level descriptions (often called silicon compilers ) were not included neither were system level design tools. 

An integrated synthesis system that covers all three synthesis levels is often referred to as a silicon compiler. In a sense, it represents the ultimate synthesis tool and the major challenge in synthesis. Such a tool would allow the design of electronic circuits from a high-level, behavioral specification with little or no human intervention. 

R.K. Brayton, R. Camposano, G. DeMicheli, R.H.J.M. Otten, and J.T.J. van Eijndhoven, e Yorktown Silicon Compiler System, in D. Gqjski, editor, Silicon Compilation, Addison-Wesley, 1988. 

R. Camposano, "Structural Synthesis in the Yorktown Silicon Compiler, in C.H. Sequin, editor, VLSVS , VLSI Design of Digital Systems, pp. 61-72, Vancouver North-Holland, 1988. 

B.M. Pangrle and D.D. Gtyski, Design Tools for Intelligent Silicon Compilation, IEEE Transactions on Computer-Aided Design, vol. CAD-6, no. 6, pp. 1098-1112, November 1987. 

Thaddeus J. Kowalski, The VLSI Design Automation Assistant An Architecture Compiler , in Silicon Compilation, Daniel D. Gajski (Editor), pages 122-152, Addison-Wesley, 1988. 

L. Stok and R. van den Bom, EASY Multiprocessor Architecture Optimisation , in Logic and Architecture Synthesis for Silicon Compilers (Proc. of the Int. Workshop on Logic and Arch. Synth, for Silicon Compilers), G. Saucier and P.M. McLellan (Editors), pages 313-328, Elsevier Science Publishers, May 1988. 

IBM s HIS d gh-Level IBM Synthesis) system includes scheduling and data path synthesis. See also IBM s Yorktown Silicon Compiler and Univ. of Karlsruhe s DSL Synthesis System / CADDY System — Camposano was previously involved with those systems. 

Also reads a text form of YIF tJCorktown Internal Eormat). IBM s Yorktown Silicon Compiler. 

IBM s V compiler produces Register- Transfer level designs, which can then passed on to the LSS system for logic synthesis. The V compiler includes scheduling and data path synthesis, and can produce high level software simulators for the designs. A subset of the language is used to produce YIF format output for IBM s Yorktown Silicon Compiler and IBM s HIS System. 

Viktors Berstis, Daniel Brand, and Ravi Nair, An Experiment in Silicon Compilation , Proc. of ISCAS 85, pages 655-658, June 1985. 

Raul Camposano, Design Process Model in the Yorktown Silicon Compiler , Proc. of the 25th DAC, pages 489-494, June 1988. 

Raul Camposano, "Structural S3mthesis in the Yorktown Silicon Compiler, Proc. ofVLSr87, pages 61-72, August 1987. 

J. Zegers, P. Six, J. Rabaey, and H. De Man, CGE Automatic Generation of Controllers in the CATHEDRAL-II Silicon Compiler , Proc. ofEDAC 90, pages 617-621, June 1989. 

H. De Man, J. Rabaey, P. Six, and L. Claesen, CATHEDRAL II A Silicon Compiler for Digital Signal Processing , IEEE Design and Test, pages 13-25, December 1986. 

Barry Michael Pangrle and Daniel D. Gajski, "Sheer A State Synthesizer for Intelligent Silicon Compilation", Proc. of icars , pages 42-45, October 1987. 

Barry Michael Pangrle, A Behavioral Compiler for Intelligent Silicon Compilation, PhD Thesis, Dept, of (Computer Science, University of Illinois, 1987. 

Daniel D. Gajski and Forrest D, Brewer, "Towards Intelligent Silicon Compilation , in Design Systems for VLSI Circuits, G. DeMicheli, A Sangiovanni-Vincentelli, and P. Antognetti (Editors), pages 365-383, Martinus Nijhoff Publishers, 1987,... 

Baher S. Haroiin and Mohamed I. Elmasiy, Ardiitectural Synthesis for DSP Silicon Compilers, IEEE Tnms. on CAD, pages 431-447, ril 1989. 

Integrated circuits—Very large scale integration—Design and construction—Data processing. 2. Silicon compilers. I. Walker,... 

The Yorktown Silicon Compiler(YSC) [Brayton87] takes a very different approach to global scheduling. The YSC schedules as many operations as possible into states, minimizing the total number of states. It then performs a separate state splitting task that divides operations in a state into two states to reduce the combinational logic delays in the longest states. 

---