Hardware Description Languages

VEiDE very-high-speed integrated-circuit hardware description language... 

The suggested procedure to arrive at this goal is presented in Fig. 3.1. It starts with the transfer of a certain microhotplate layout into a geometry model for a complex FEM simulation. This step is shown in Fig. 3.2 and will be explained in more detail in one of the next sections. A complex 3-d FEM simulation is then performed. The results of this simulation are used to produce a lumped-element model. This model is translated into a hardware description language (HDL). Using the resistances of the device elements such as the heater resistance, Rheat> and the resistance of the temperature sensor, Rx. co-simulations with the circuitry can be performed. 

D. Gibson, H. Carter, and C. Pm-dy. The Use of Hardware Description Languages in the Development of Microelectromechanical Systems , Analog Integrated Circuits and Signal Processing 28 (2001), 173-180. 

IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Std 1364-1995, IEEE, 1995. 

Thomas D. and P. Moorby, The Verilog Hardware Description Language, Kluwer Academic, MA, 1991, ISBN 0-7923912-6-8. 

The Verilog Hardware Description Language, often referred to as Verilog HDL, is an IEEE standard (IEEE Std 1364). The language can be used to describe the behavior, sequential and concurrent, or structure of a model. It can support the description of a design at multiple levels of ab-... 

H.A. Mantooth, M. Fiegenbaum, Modeling with an Analog Hardware Description Language, Kluwer, 1995. 

Inti IFIP Conference on Computer Hardware Description Languages and their Applications (CHDL 95). Elsevier, 1995. 

CGH 93] Edmund Clarke, Orna Grumberg, Hiromi Hiraishi, Somesh Jha, David Long, Ken McMillan, and Linda Ness. Verification of the futurebus+ cache coherence protocol. In D. Agnew, L. Claesen, and R. Camposano, editors. Proceedings of the 11th International Conference on Computer Hardware Description Languages and their Applications, 1993. 

CSZ97] Francisco Corella, Robert Shaw, and Cui Zhang. A formal proof of absence of deadlock for any acyclic network of PCI buses. In Hardware Description Languages and their Applications, pages 134-156. Chapman Hall, 1997. 

IEEE Standard Hardware Description Language based on the Verilog HDV IEEEStandardl364-1995,1995... 

Thomas D. E., Moorby P. R. " The Verilog Hardware Description Language ", Second edition, Kluwer, 1995... 

VHSIC Hardware Description Language (VHDL) is a widely used hardware description language which has become a standard in many domsuns. A common traditional use of VHDL has been to construct VHDL descriptions modeling the hardware design and then simulate the VHDL program to show that it meets a set of informal specification criteria from which test vectors have been generated. However, this approach is often insufficient in critical applications where it is desirable to prove that the VHDL description meets a set of formally specified correctness criteria, and a formal semantics of VHDL is thus needed. 

The aim of this paper is to set out a semantic model for VHDL-AMS, the analog and mixed-signal extension to the IEEE standard hardware description language VHDL (IEEE 1994). VHDL itself supports only digital hardware and discrete time. VHDL-AMS is being developed by IEEE working group 1076.1. 

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