Cu Interconnections on Chips

The clrange from Al to Cu interconnects, mentioned above, required concurrent significant changes in the fabrication process, from metal-RIE to dielectric-RIE (reactive ion etching). The introduction of copper interconnects creates, in addition, new problems in tire fabrication of those intereoimects on chips. The most important of tlrose mentioned briefly above, are the possible diffu- 

Metal-RIE process was/is used in the fabrication of Al inter-coimects on chips. This process is depicted in four steps in Fig. 2. The first step in the metal-RIE process is sputter deposition of a blanket thin film of Al (or Al alloys, such as Al-Cu, Al-Si) over a planerized dielectric (e.g., silicon dioxide). In the next step, the unwanted metal is etched away by reactive ion etching (RIE) through a photoresist mask. The features produced this way are separated, electrically isolated, metal Al conductor lines. In the RIE process chemicaly active ions such as F or Cl bombard the Al surface and form volatile aluminum fluorides or chlorides, which are then pumped away in the vacuum system. After etcliing, a dielectric is deposited in such a fashion that it fills the gaps between the lines as well as above them. In the last step, the dielectric is planarized using the chemical mechanical polishing (CMP) technique.  

The selective Cu deposition process was suggested, among others, by Ting and Paunovic. This is an alternative process to 

This process is also known as through-mask deposition process. The first step in tliis procedure is the deposition of a Cu seed layer on a Si wafer followed by deposition and pattern of a resist mask to expose the underlyings seed layer in vias and trenches. In tlie next step. Cu is deposited to fill the pattern. After this the mask is removed, the surrounding seed layer is etched, and the dielectric is deposited. Electroless Cu deposition was suggested for the blanket and selective deposition processes.  

One important difference between the damascene and the plating through mask procedures is the way the trenches and vias are filled with electrochemically deposited Cu, either tlirough electro or electroless techniques. In multi-level metal slruclures. the vias provide paths for connecting two conductive regions separated by inter-level dielectric (ILD). In a damascene process the Cu deposit grows from the active bottom and the sidewalls, as shown in Fig. 7a. 

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Multilevel Cu interconnections on chips are now fabricated using a dielectric-RIE process. In this process, a blanket Cu deposition is followed by chemical-mechanical polishing (CMP) of Cu [99], This approach... 

Deposition of Cu Interconnections on Chips Diffusion Barriers and Seed Layer. ... 

The required degree of understanding of the physical properties of metal thin films used for interconnects on chips is illustrated by the following example. It was found that the performance of conductors on chips, A1 or Cu, depends on the structure of the conductor metal. For example, Vaidya and Sinha (10) reported that the measured median time to failure (MTF) of Al-0.5% Cu thin films is a function of three microstructural variables (attributes) median grain size, statistical variance (cr ) of the grain size distribution, and degree of [111] fiber texture in the film. 

Copper introduces new problems in the fabrication of interconnects on chips, the most important of which is the diffusion of Cu into Si, Si02, and other dielectrics (4),... 

It is seen from the discussion above that Cu is electrodeposited in vias and trenches on a bilayer a barrier metaVCu seed layer. When the barrier layer is composed of two layers (e.g., TiN/Ti), Cu is electrodeposited as a trilayer a barrier bilayer/Cu seed layer. This type of underlayer for electrodeposition of Cu raises a series of interesting theoretical and practical questions of considerable significance regarding the reliability of interconnects on chips. In Section 19.1 we have noted that interconnect reliability depends on the microstructural attributes of electrodeposited Cu (for Cu-based interconnects). These microstractural attributes, such as grain size, grain size distribution, and texture, determine the mechanical and physical properties of the thin films. Thus, one basic question in the foregoing series of questions is the problem of the influence of the underlayer barrier metal on the microstructure of the Cu seed layer. The second question is the influence of the microstructure of the Cu seed layer on the structure... 

One major recent advance in silicon-based semiconductor industry is the development of copper interconnects on chips. This new technology replaces the traditional aluminum or aluminum alloy (e.g. Al—Cu) conductors produced by physical vapor deposition (PVD) with copper conductors manufactured by electrodeposition. Copper has been replacing aluminum since 1999 owing to its low bulk electrical... 

The metal-RIE process is used in the fabrication of Al interconnects on chips. In this process, a blanket thin film of Al (or Al alloys, like Al—Cu, Al—Si) is deposited and then etched in a reactive plasma (RIE) through a photoresist stencil. After RIE, a... 

One of challenges in the fabrication of interconnections on chip is the electrodeposition of Cu in vias of small diameter (<0.2 pm) and high aspect ratio, height/width >2. Modeling of these... 

Copper introduces new problems in the fabrication of interconnects on chips. The most important one is the diffusion of Cu into Si, SiC>2, and other dielectrics [92], and reaction of Cu with Si forming silicides [109]. Diffusion of Cu through Si results in the poisoning of devices (transistors) and diffusion through SiC>2, dielectrics, leads to the degradation of dielectrics, which can result in... 

The required depth of understanding of the physical properties of metal thin films used for interconnects on chips may well be illustrated by the following example. It was found tliat the performance of conductors on chips, Al or Cu, depends on the morphol-... 

Figure 1.3 shows an example module with thin-film interconnects on a low-temperature cofired ceramic (LTCC) substrate [32]. This module measures 81 X 55 X 1.88 mm and has a 14-layer cofired LTCC substrate with silver conductor and 6-layer thin-film interconnects (three on the top and three on the bottom) using Ti/Cu and benzocyclobutane (BCD) structure. A microprocessor is connected to 2 memory chips and over 140 passive components through about 4000 nets. 

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