Solder bumps

As an attractive alternative to the vidicon the array of elements can be connected directly to individual voltage detectors on a silicon integrated circuit (usually referred to as a ROIC read-out integrated circuit ) via solder bumps . The resulting signals can then be electronically processed to yield a picture in the standard way. Fig. 7.13 shows a section through part of such an imaging array. 

Another new method of solder bumping is based on injection-molded solder technique. This technology, which is known as C4NP (C4-new process) was developed... 

Fig. 14.3 Process steps involved in the C4NP technology. Wafers with BLM and solder-fiUed molds are processed in parallel and joined together. Solder bumps are thus transferred to the wafer. Inset Solder balls formed by C4NP process. Ref. [23] reproduced with permission of the Electrochemical Society...

Parasitics are an important factor in the decision for monolithic integration versus two-chip solutions. Owing to their small dimensions, the practically achievable sense capacitance in many surface micromachined devices with typical 2 pm gaps and film thickness is often 100 fF or less. Since chip-to-chip interconnections, even using solder bumps, add at least 1 pF parasitic capacitance, on-chip electronics is usually required to achieve the highest possible sensitivity. Bulk-mi-cromachined devices have much higher sense capacitance in this case a two-chip solution may not incur a resolution penalty. 

J.I. Han, S.I. Hong, "Nickel electroless plating process for solder bump chip on glass technology," Jpn. J. Appl. Phys., Vol. 36, 2091-2095 (1997). 

Figure 11-10. A 60-nm solder bump deposited as a liquid onto copper using ink-jet printing technology. Left is model...

Solder bumps as small as 25 pm on 35 pm have been demonstrated. Figure 11-14 also shows solder towers that can be printed by dispensing a burst (more than one) of drops that stack up as tower. 

Figure 11-15 shows eutectic solder bumps placed onto a 18 x 18 test substrate with 100-pm diameter pads on 250 pm centers. The solder volume deposited per pad is equivalent to a drop diameter of 100 pm. The solder bumps acquire the shape shown in Figure 11-15 is a result of rapid solidification [18]. The bumps were placed at the rate of 400 s by raster-ing the substrate in the horizontal direction of the rows of solder bumps. 

Figure 11-15. 100-pm solder bumps placed on 10-pm pad at 250 pm centers at 400 bumps... 

Flip-chip devices have solder bumps, other metal bumps, or even conductive adhesive bumps on the face of the device for I/O connections. During assembly, the devices are flipped face down, then mated and bonded to corresponding solder or metal pads on the package or interconnect substrate. In the quest to eliminate tin-lead solders, electrically conductive epoxy adhesives are beginning to be used for the bumps. 

Adhesives used to fill spaces underneath a flip-chip device or BGA package must flow readily and rapidly when dispensed at the edges of the chip in order to completely fill the gap and free space surrounding the solder bumps. To be effective, the adhesive must be drawn into the narrow space by capillary action. The theory behind underfilling is based on capillary-flow behavior between closely spaced parallel plates (Fig. 2.5) by considering the drop in pressure (p) across a liquid-vapor interface ... 

The volume of underfill must be controlled to assure complete filling beneath the die and some filleting around the die. A complex combination of factors (gap height, contact angle, viscosity, wettability) affects the amount of underfill required for complete coverage. The volume of underfill (V) is calculated based on the volume of free space under the die (Vc), the volume of the solder bumps (Vb), and the fillet volume (Vf) or V=Vc — Vb +... 

A third approach to underfilling involves applying an insulative thermoplastic preform (film) prior to attaching the device. Under pressure and heat, the preform softens and flows around the solder bumps, then solidifies quickly on cooUng. The devices may then be solder reflowed to make the connections or the preform may be formulated to flow and encapsulate the solder during solder reflow. Table 5.6 lists some commercially available preforms used as underfills. Anisotropic film adhesives have also been used as underfill preforms, in which case z-direction conductive paths are formed beneath the solder bumps at the same time that the rest of the insulating film flows and cures around the bumps. Anisotropic paste adhesives can be similarly used (Figure 5.11). 

In a similar process, known as polymer-film interconnect (PFI), an insulative thermoplastic film is laminated over the devices at the wafer stage, and vias are opened over the bonding pads using a laser. At that point, either the normal solder bumps can be formed or a silver-filled conductive adhesive can be stencil printed into the vias to form polymer bumps. After printing, the epoxy is B-staged and the flip-chip devices are diced. In assembly, the devices are heated to a temperature that completes the cure of the B-staged bumps and simultaneously reflows the thermoplastic underfill material. 

UF-3400/ 3MCo. No-flow, unfilled epoxy resin - FUp-chip/BGA or CSP assembly and CSP bonding to PWBs (tin/lead eutectic solder bumped devices) Automated dispensing (22- gauge needle) CSP assembly and FCOB and CSP bonding to laminates. 

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