Chip-package interconnect

With the conventional technology, ICs are mounted individually in plastic or ceramic single-chip packages (SCPs), such as dual-in-line packages (DIPs) or chip carriers, and the SCPs are interconnected on printed wiring boards (PWBs). The number of pins on SCPs has increased significantly, and line widths on PWBs, like IC feature sizes, have followed a historical downward trend (2). However, the basic SCP-on-PWB approach has remained predominant. 

TFML interconnections can be fabricated on a variety of substrates, including ceramics, metals, or silicon wafers. An approach proposed by Honeywell (8), which uses a multilayer co-fired ceramic substrate, is illustrated in Figure 1. The co-fired ceramic substrate is 50-100 mm square, with internal metal layers for power and ground distribution and pins brazed to the bottom for connection to a PWB. Metallized strips on the bottom of the substrate contact the PWB to conduct heat away from the package. A metal seal ring around the perimeter of the substrate permits hermetic sealing to provide mechanical and environmental protection for the chips and interconnections. 

Computers, microprocessors, and other microelectronic devices could not exist as we know them today without the technology of depositing thin metal or alloy films with fine lithographic patterns. For example, in a computer, the individual transistors that make up an integrated circuit must be electrically interconnected by a complex network of conducting lines and vias that are deposited above the semiconductor layers. Furthermore, the chips are joined to multi-chip packaging modules, a process in which many electrical connections are simultaneously established by solder balls. 

The most often discussed application of SPAs is optical interconnection. All applications of these arrays involve optical interconnection in one way or another, but the term optical interconnection most often refers to optical data channels between electronic processors and devices. This includes data transfer between machines, racks, boards, and chips. SPAs are being developed for optical interconnection at the board and chip level where the demand is very high for the dense packaging of the electronic and optical devices. Figure 2 illustrates two of several envisioned configurations for board-to-board and chip-to-chip optical interconnection. 

Xuefeng Z, Ryu S-K, Huang R, Ho PS, Liu J, Toma D. Impact of process induced stresses and chip-packaging interaction on reliability of air-gap interconnects. In Interconnect technology conference, 2008. IITC 2008. International, 1—4 June 2008 2008. p. 135—7. 

For interconnecting IC substrates with hundreds of I/O terminals, a single layer of microvia holes may not be sufficient to satisfy interconnection requirements. Double, triple, or even quadruple microvia hole layers may be necessary whether the board is a motherboard or a chip package substrate. When microvia holes are made only between adjacent layers (see Fig. 22.6), all three microvia processes— photovia, plasma via, and laser via—can be used. However, when a design requires microvia holes that must connect beyond adjacent layers—such as LI and L3 (skipvia)—laser via processing is the only practical option. 

Sporadic Failures. The failure of solder joints attached to ENIG is occasional. In the reference literature, there are numerous reports showing that solder joints on the ENIG finish are reliable (e.g.. Ref 88, 89). ENIG seems less of a reliability problem for solder joints in flip chip packages (the first-level interconnect) than in... 

Besides die attachment, ICAs are utilized in surface mount and flip-chip packages as alternatives to traditional solders. Due to their low surface tensions, ICAs are not suitable for wave soldering (Ref 6). Despite the advantages of ICA interconnection, the wide use of this technology has not been adopted by the electronics industry. The main concern is long-term reliability. 

---