Multichip Packages

Multichip Packaging. A solution to these problems is to mount a number of ICs closely together on a common substrate within an MCP. The obvious advantages of the MCP are the reduction in the overall size and weight of the package and, thus, the reduction in the size and cost of the system. The reliability of the system is also improved, because the chip-to-chip interconnections can be accomplished within the package, which reduces the number of package-to-board connections. 

Figure 7. Metallization pattern for the top layer of a 2.25 by 2.25 in. (5.1 by 5.1 cm) multichip package, with chip footprints, I/O pads, and other surface...

Thick-Film Multilayer. Thick-film multilayer technology has been used for many years to fabricate hybrid circuits that interconnect small-scale ICs or discrete components on a ceramic or metal substrate (67-70). This technology has also been used for multichip packaging of more highly integrated ICs for large computer applications. 

The top of Figure 12 shows a thick-film multilayer multichip package used in a mainframe computer (Honeywell DPS 88) (71), and the bottom shows the signal lines on an internal metal layer in this package. The package... 

In the multichip package, a variety of pretested chips (e.g., bipolar, MOS, and GaAs) and discrete components (decoupling capacitors and termination resistors) may be mounted on the high-density interconnection substrate. This approach is sometimes termed hybrid-wafer-scale integra-... 

Figure 22. Multichip package for electrooptical-signal-processing applications, with TFML interconnections on a ceramic substrate housed in a metal flatpack. (Reproduced from reference 80. Copyright 1987 American Chemical Society.)...

Figure 23. Multichip package for a supercomputer. Top, unpopulated substrate with TFML copper-polyimide interconnections on a 100 by 100 mm multilayer ceramic substrate bottom, cross section of interconnection structure and flip-TAB carrier. (Reproduced with permission from reference 81. Copyright 1985 Institute of Electrical and Electronics Engineers.)...

The chips can be electrically bonded to the multichip package by wire bonding or tape automated bonding (TAB). 

Figure 1. Proposed approach for multichip packaging using thin film multilayer Cu/polyimide interconnections.

Honeywell has also demonstrated TFML interconnections in a multichip package for digital image processing applications (9). 

Figure 10. Multichip package with TFML interconnections housed in a metal flatpack.

Figure 1.10 High-density multichip packaging flip-chip-attached die on ball-grid-array...

Multichip packaging involves the attachment and interconnection of a variety of chip devices on an interconnect substrate that may be single layer or multilayer. There are two basic types of multichip packaging hybrid microcircuits and multichip modules. 

Pillion RA, Neugebauer CA. High density multichip packaging. Solid State Technol. Sep. 1989. Hybrid Supplement. 

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