Deposition of Cu Interconnections on Chips

Multilevel Cu interconnections on chips are now fabricated using a dielectric-RIE process. In this process, a blanket Cu deposition is followed by chemical-mechanical polishing (CMP) of Cu [99], This approach 

Selective Cu deposition process was suggested as an alternative process for the fabrication of multilevel Cu interconnections (Fig. 38). This process is known as through-mask deposition process [100]. The first step in this process is the deposition of a Cu seed layer on Si wafer then a resist mask is deposited and patterned to expose the underlying seed layer in vias and trenches. In the next step, Cu is deposited to fill the pattern. After the Cu deposition mask is removed, the surrounding seed layer is etched, and the dielectric is 

There is a basic difference between the damascene and the plating-through-mask processes in the way in which the trenches and vias are filled with electrochemically deposited Cu, either through electro- or electroless technique. In multilevel metal structures, vias provide 

One of challenges in the fabrication of interconnections on chip is the electrodeposition of Cu in vias of small diameter ( 0.2 pm) and high aspect ratio, height/width 2. Modeling of these 

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Deposition of Cu Interconnections on Chips Diffusion Barriers and Seed Layer. ... 

One major recent advance in silicon-based semiconductor industry is the development of copper interconnects on chips. This new technology replaces the traditional aluminum or aluminum alloy (e.g. Al—Cu) conductors produced by physical vapor deposition (PVD) with copper conductors manufactured by electrodeposition. Copper has been replacing aluminum since 1999 owing to its low bulk electrical... 

The metal-RIE process is used in the fabrication of Al interconnects on chips. In this process, a blanket thin film of Al (or Al alloys, like Al—Cu, Al—Si) is deposited and then etched in a reactive plasma (RIE) through a photoresist stencil. After RIE, a... 

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