Chip carrier, design

The commercial LCP/PPS blend is designed for injection molding complex electronic parts, chip carriers, sockets and cod bobbins. It is very likely that due to its low melt viscosity, LCP still forms the continuous phase, while PPS may simply be present as a dispersed filler along with the glass fibers. Very httle information about this blend has been pubhshed. 

Hermetic packages, such as the older flat pack design or ceramic leadless chip carriers (CLCCs), are used in harsh applications (such as military and space applications) where water vapor and contaminants can shorten the life of the device. Thus they are used in mission critical communication, and navigation and avionic systems. The reliability of CLCC package connections can be further improved by the attachment of leads to the connection pads, to eliminate differences in the thermal coefficient of expansion between the parts and the circuit board material. 

Leaded ceramic chip carrier (LDCC), leaded ceramic chip carrier packages include JEDEC types A, B, C, and D. Leaded type B parts are direct soldered to a substrate. Leaded type A parts can be socketed or direct soldered, and include sub-categories leaded ceramic, premolded plastic, and postmolded plastic (which are not designated as LDCC devices). 

MQFP—Metal Quad Flatpack. Sometimes used to refer to a plastic metric quad flat pack (such as Harris Corporation, Harris sold its semiconductor operations, now known as Intersil Corp.). MQuad, designed by the Olin Corporation, a high thermal dissipation aluminum package available in plastic leaded chip carrier (PLCC) and QFP packages (with 28-300 leads, and clock speeds of 150 MHz) (see Fig. 8.137). 

The discussion of lead properties of course does not apply to leadless devices such as leadless ceramic chip carriers (LCCCs). Design teams using these and similar packages must understand the better heat transfer properties of the alumina used in ceramic packages and must match coefficients of thermal expansion (CTEs or TCEs) between the LCCC and the substrate since there are no leads to bend and absorb mismatches of expansion. Use of ceramic devices may lead the design team to consider the use of Low Temperature Co-fired Ceramic (LTCC) substrates and assembly technologies XXX. 

Bak, D. J. Foam Sheet Joins Chip Carrier, Circuit Board. Design News, pp. 112-14, Feb. 1989. 

Some device designs call for wirebonding directly to the PCB or laminate chip carrier. In general, most surfaces are wirebondable with aluminum wire. A1 wirebonding may be impossible... 

Use of silicone gel in this way is illustrated in Fig. 3.5. Chip carriers to JEDEC design are filled with the uncured liquid gel by meter-mix application in-line and heated in a tunnel through which the conveyor strip passes to cure the gel. This then provides protection to the chip and its leads against both corrosion and mechanical stress caused by differential thermal expansion of the package components. 

In particular, these materials can be extruded and injection moulded offering the potential for low cost volume production. In the case of moulded boards, the advantages include the ability to mould design features such as holes, chip carrier cavities and standoffs. The three most important classes of high temperature thermoplastics are polysulphones, polyphenylene sulphides, and the very recently introduced polyetherimide (Ultem). 

DFR design for reliability PLCC plastic leadless chip carrier... 

In assemblies utilizing lead-free solder, work must be performed to ensure that the flux, underfill, component, and PCB system is compatible. For an underfill to be effective, the underfill must bond to the die and chip carrier surfaces. Current underfill systems are designed to be compatible with flux systems for Sn-Pb solder, which may not be the case with a lead-free solder. An additional concern for underfilled systems is exposure to reflow temperatures. For example, flip-chip BGA components may experience several reflow cycles after the underfill step. The higher processing temperatures experienced during lead-free soldering can have detrimental effects such as delamination of the underfill material from the chip carrier or die surface. 

There has recently been a renewed interest in Sn whiskers because of the worldwide conversion to Pb-free solders and finishes in electronic manufacturing. Finishes are applied to printed circuit boards (PCBs) and to the lead frames used to connect device packages to printed circuit boards. Lead frames are typically made of a copper (Cu) or iron-nickel (FeNi) alloy plated with a Sn-Pb alloy. Fig. 5 is a schematic diagram of a lead frame cross section bonded to a chip-carrier package. The surface finish of the lead-frame leg is designed to provide surface passivation and enhanced solderability. Typical Pb-free surface finishes are eutectic Sn-Cu or pure Sn. Tin(Sn) whiskers readily grow on high-Sn content finishes under certain conditions. 

Adhesives are used to attaeh the ehip to the earrier and the carriers to an interconnect substrate. In the past decade, there has been a proliferation of designs and configurations for CSPs, and they have become the preferred method of packaging ICs having up to 500 I/Os. One design is shown in Fig. 1.13. Chip-scale packages are classified as four general types. 

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