PLANAR-SURFACE

Stylus profilometry is a very simple and powerful tool in CMP. Profilometry can be used to determine the surface planarity change before and after CMP. Basically, in this technique, a stylus scans across a pattern feature in contact with a wafer, while the Z motion (height) of the stylus is monitored. This Z motion signal reflects the surface topography scanned. 

In this work, a framework of the SSL theory for diblock copolymer melts confined in ring-like curved surfaces has been proposed. When the curvature approaches to zero, it reduces to the well-known SSL theory for the parallel lamellar phases. In the case of the equal confined thickness to the exterior radius, it can also be extended to the system with a nanopore confinement. Moreover, the Helmholtz energy of the concentric cylinder barrel, sector column and CMSC phases in 2D confinements based on this SSL theoretical framework can be evaluated in the convenient manner. The calculated results show that the diblock copolymer melts exhibit a layer-type transition with a similar mechanism, regardless of ring-like curved surfaces, planar surfaces, and nanopores. 

Applied substrates require homogeneous and planar surfaces. Planar supports allow accurate scanning and imaging, which rely on a uniform detection distance between the microarray surface and the optical device. Planar solid support materials tend to be impermeable to liquids, allowing for a small feature size and keeping the hybridization volume to a minimum. Flat substrates are amenable to automated manufacture, providing an accurate distance from photo masks, pins, ink-jet nozzles and other manufacturing implements. The flatness affords automation, an increased precision in manufacture, and detection and impermeability. Table 1 shows frequently used support materials... 

As discussed earlier, electrochemical dissolution proceeds under dynamic conditions when the applied anode potential is relatively low that is, the process is dominated by electrochemical reactions, and potential and current obey Ohm s law, as expressed in Equation 10.9. Under these conditions, surface planarization can be achieved by electrochemical dissolution if the interelectrode distance and anode surface roughness have the same order of magnitude. As illustrated in Fig. 10.7, the distance (f) between the anode and... 

Required planarity The planarity requirements to fulfill the extremely strong DOF demands in microelectronics can only be achieved by employing CMP for planarization. In microfabrication, CMP is used when high topography has to be smoothed, usually with much relaxed planarity requirements. One exception is the manufacturing of optical microsystems (optoMEMS, MOEMS), where the surface planarity demands as a rule of thumb are typically less than a tenth of the wavelength (<2/10). 

Advanced metallization schemes are required to obtain the performance benefits of scaling device dimensions into the sub-0.5 pm regime. This section discusses the origin of the interconnect delay and impact on IC electrical performance. Methods of reducing interconnect delay will be discussed, including MLM and the use of new metal and ILD materials. As additional metal layers are added, surface planarization requirements increase. This section discusses planarity requirements while subsequent sections discuss planarization schemes, including CMP. 

As interconnection dimensions shrink and the number of metal layers grows, the need for surface planarity increases. Wafer... 

Figure 2.2 Degrees of surface planarity (a) unplanarized, fl)) surface smoothing, (c) local planarization, and (d) global planarization.

Planarization Rate Planarization rate is the time it takes to reduce the topography of the wafer surface to the desired level. Several metrics of planarity are reviewed in Section 2.2. In the CMP of oxide and other BLDs, because the end goal is surface planarization not simply material removal, the planarization rate is as important a metric as polish rate. 

One of the first and die most widely used CMP process, aside from the final step in the preparation of silicon wafers, is oxide CMP for back-end planarization after the initial oxide ILD deposition and between metal levels. As a result, oxide CMP is the most mature process, with the most fundamental studies having been performed in this area. Indeed, much of our understanding of the CMP of metals and other materials is derived from our understanding of oxide CMP. This chapter first presents the current understanding of the oxide CMP fundamentals. The discussion includes the mechanisms of both mato-ial removal and surface planarization. The second part of the chapter is devoted to the practice of oxide CMP, including reported results on planarization and polish rate performance of oxide CMP processes in industry. In addition, process integration, cost of ownership, manufacturability, and yield issues will be discussed. 

However, for planarization, polish rate is not the only criterion. Indeed, the most important performance indicator is planarization ability. Figure 5.13 shows the polish rate of the high areas and the low areas vs. time for both ceria and silica abrasives. For both slurries, the polish rates of the high areas and the low areas converge, with polish time decreasing the planarization selectivity (selectivity is the polish rate in the high areas divided by the polish rate in the low areas). This is to be expected, however as the surface planarizes, the difference in height between the low areas... 

A surface planarized by CMP may have many undesirable features on or within the surface (a) particles — from the slurry or from the abraded surface and even from the surroundings —, (b) chemical contamination from the slurry and/or chemical crosscontamination resulting from different materials present on the surface (e.g., during CMP of inlaid metal), (c) physical damage, like scratches and pits, (d) stress, in the polished surface, associated with the compaction of the top few atomic layers, and (e) surface inclusions formed due to reactions with abrasive particles or pad materials. An effective cleaning process must take care of all of these. This would suggest that a possible sequence of several physically or chemically induced cleaning processes (such as those mentioned in Chapter 1) may be needed. 

For instance, what model should be assumed for the atomic structure of a surface The simplest picture of a surface is a planar terrace, a static array of passive adsorption sites. For a crystal, such terraces are slices through the bulk stacking sequence, a cleavage of the bulk. Is the planar terrace a reasonable model Some unrelaxed bulk terminations are polar and thus inherently unstable (see below). But for non-polar surfaces, planarity is often favoured in order to minimise the surface energy (Section 3). Thus on the timescales of diffraction techniques, such as LEED and XAFS, many surfaces are indeed observed to be... 

FIGURE 5.18 Proposed model for the nanotopography impact (a) dependence of surface planarization efficiency on the abrasive size and surfactant and (b) relationship between film surface flatness and oxide thickness deviation after CMP. 

These process steps, as practiced for the trench isolation process, are either new or modifications or extensions of previously practiced processes used for other aspects of device fabrications. Consequently, several of these steps did require general process development on an individual basis, prior to their integration into the overall process. Some of the efforts have resulted in new basic knowledge in the area of reactive ion etching (RIE) and chemical vapor deposition, surface planarization with resist materials, and thermal oxidation or nonplanar silicon surfaces. The author has previously presented various aspects of these process activities (4-8), as applied to the bipolar device technology. 

The planarity of the surface above a narrow CVD-filled trench may be quite good, provided a sufficient amount of CVD material has been deposited. The specific planarity will depend directly on the trench width and the CVD film thickness. This relationship is shown in Figure 20. Surface planarity will not be achieved for wider trenches. Such major surface irregularities cannot be tolerated as a final surface structure, and a post-CVD surface planarization technique must be employed to assure a sufficiently planar surface prior to a subsequent back-etching process step. 

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