Interconnection delay

The two key components in interconnect delays include the inherent resistance (R) of the metal lines and the capacitance (C) of the dielectric material in between the lines. The so-called RC delay is defined as the time required for the voltage at one end of a metal line to reach 63 % of its final value when a step input is presented at the other end of the line [18] ... 

Advanced metallization schemes are required to obtain the performance benefits of scaling device dimensions into the sub-0.5 pm regime. This section discusses the origin of the interconnect delay and impact on IC electrical performance. Methods of reducing interconnect delay will be discussed, including MLM and the use of new metal and ILD materials. As additional metal layers are added, surface planarization requirements increase. This section discusses planarity requirements while subsequent sections discuss planarization schemes, including CMP. 

From Equation (2.3), the RC delay is directly proportional to the dielectric constant of the ILD. By switching from oxide-based ILD to a low e, ILD material, significant gains may be obtained in decreasing the interconnect delay. In addition, lowering dielectric constant lowers cross talk due to capacitive coupling between adjacent metal lines and power dissipation which is given... 

One of the parameters for measuring device performance is interconnect delay or the time constant. ... 

The interconnect delay is due to the capacitance C and resistance R associated with metal lines. The resistance of a line is given by ... 

Fig. 8 Gate and interconnect delay versus feature size. Interconnect delay is shown for repeater spacings of 3000 pm. (Some data adapted from Ref )...

As the circuit features shrink, the interconnect delays start to get very large very fast. Some manufacturers have asserted that production of circuits faster than 600 MHz could not be achieved with conventional metals and dielectrics. Since circuit speed is one of the fundamental drivers of circuit market success, these barriers had to be surmounted. The resistance of an interconnect line, like the capacitance, is derived from the design geometry of the circuit and a choice of the material composition of the line. Of the three dimensions (Figure 1.11a), the layout design of a circuit will determine how far a transistor is from the next circuit element with which it needs to... 

The overall circuit delay will be a combination of the transistor switching delay (which gets smaller with smaller feature sizes), and the interconnect delay (which gets larger with smaller feature sizes). The choice of the... 

Alpert CJ, Devgan A, Quay ST (1999) Buffer Insertion with Accurate Gate and Interconnect Delay Computation, DAC 1999, pp 479-484... 

Buffering has become indispensable in timing closure and cannot be ignored during interconnect delay estimation [11-13]. Therefore to calculate new locations of movable gates, one must adopt a buffering-aware interconnect delay model that accounts for future buffers. We found that the linear delay model described in [13, 14] is suited to physical synthesis applications. In this model, the delay along an optimally buffered interconnect is... 

Abou-Seido A, NowakB, Chu C (2004) Fitted Elmore delay a simple and accurate interconnect delay model. IEEE Trans VLSI Syst 12(7) 691-696... 

---