Inlaid Metal

The ideal deposition process would leave a perfectly flat surface. That does not happen, so a planarization process is required to maintain depth of field requirements. For a dielectric planarization process, the ideal planarization process would remove only material in the up areas and remove no material in the down areas. Metal CMP involves the removal of metal overburden, leaving filled plugs or vias (single damascene) or filled vias and inlaid metal lines (dual damascene) with no removal of metal in the inlaid region and no removal of dielectric. 

Inlaid metal patterning schemes were first used in the formation of tungsten studs to fill contact and via holes. In this application, a blanket tungsten film is deposited by CVD thick... 

In addition, several issues arise with the use of either RIE etch back or CMP to remove the metal from on top of ILD. Dual layw inlaid metal schemes have been demonstrated for tungsten, aluminum, copper,and gold metallization systems. 

Figure 6.3 Formation of inlaid metal lines and studs.

Key to the success of inlaid metal formation via CMP is the planarizing ability of the process. One method for achieving good... 

Figure 7.7 (a) Ideal surface profile of an inlaid metal line. Removal of... 

The need for CMP planarization of polymer ILDs may be avoided through the use of inlaid metal schemes. As discussed in Chapter 6, inlaid metal schemes maintain the global planarity imposed in the first ILD layer so that only one ILD polish need be performed. If SiOj is used as the first ILD, then subsequent polymer ILD layers need not be polished directly and the problems of polymer CMP can be partially averted. However, CMP of the metal must still be performed at each layer, and even when the polymer is not directly connected during the metal CMP step, normal and shear stresses may be transmitted through the metal film. The polymer films must be mechanically stable enough to withstand die stresses involved. 

A surface planarized by CMP may have many undesirable features on or within the surface (a) particles — from the slurry or from the abraded surface and even from the surroundings —, (b) chemical contamination from the slurry and/or chemical crosscontamination resulting from different materials present on the surface (e.g., during CMP of inlaid metal), (c) physical damage, like scratches and pits, (d) stress, in the polished surface, associated with the compaction of the top few atomic layers, and (e) surface inclusions formed due to reactions with abrasive particles or pad materials. An effective cleaning process must take care of all of these. This would suggest that a possible sequence of several physically or chemically induced cleaning processes (such as those mentioned in Chapter 1) may be needed. 

In inlaid logic devices there is a move away from oxide to metal CMP for more levels of build. However, the process control required for the oxide/W polish levels is tighter because of the requirement of a high degree of planarity from the upper inlaid metal layers. For Cu, a tight polish window with controlled over/under polish has to be maintained at all metal levels for a successful multilevel structure build. 

The name damascene derives from a technique of making inlaid metals that originated in ancient Damascus, now in present day Syria. See, for example, P. Singer, Making the move to dual damascene processing, Semiconductor Int, pp. 70 82 (Jan. 1999). 

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