Multilevel metal structures

There is a basic difference between the damascene and through-mask plating processes in the way the trenches and vias are filled with electrochemically deposited Cu, through either an eiectrodeposition or an electroless technique. In multilevel metal structures, vias provide a path for connecting two conductive regions separated... 

Oxidation of Silicon. Silicon dioxide [7631-86-9], Si02, is a basic component of IC fabrication. Si02 layers are commonly used as selective masks against the implantation or diffusion of dopants into silicon. Si02 is also used to isolate one device from another. It is a component of MOS devices, and provides electrical isolation of multilevel metallization structures (12). A comparison of Si and Si02 properties is shown in Table 1. 

Turley, A.P. and Herman, D.S., LSI Yield Projections Based Upon Test Pattern Results An Application to Multilevel metal Structures . IEEE Trans, on Parts, Hybrids, and Packaging, Volume PHP-10, no. 4, pp. 230-234, December (1974). 

Figure 5-4. A schematic drawing of a multilevel metallization structure made possible by planarization.

Pinhole density is another property of interest in defining insulation integrity. It was indirectly assessed from the number of shorts in a statistical number of probed die where the die was a multilevel test structure consisting of TiWAu-polyimide-TlWAu with 3275 crossovers of first and second metal per die. The results indicated that the probability of a short in a crossover for 1.2 y thick PI2545 was 1 in 133,333. 

In addition to the multilevel metallization and formation of interconnects, anodic processing of A1 was employed for the fabrication of integrated passive components thin film capacitors and inductors.56,57 For example, localized porous-type anodization of A1 films was used to convert 20- am-thick A1 to the dielectric layer of porous AI2O3 and to define metal-dielectric-metal structures.56 The... 

The processes of planarization is vital for the development of multilevel structures in VLSI circuits. To minimize interconnection resistance and conserve chip area, multilevel metallization schemes are being developed in which the interconnects run in three dimensions. Figure 5-4 shows a schematic of the multilevel metallization made possible by planarization. 

Fig. 6. Schematic of a cross section of a typical multilevel CMOS (complimentary metal oxide semiconductor) integrated circuit structure.

Multilevel structures consisting of alternating metal and dielectric layers are necessary to achieve Interconnection in high density or VLSI circuits using either MOS or bipolar technology. 

The function of the interlevel dielectric of the multilevel structure is three-fold (1) it must provide planarization of underlying topography while allowing high resolution patterning of via holes necessary for contact between metal layers, (2) it must provide insulation integrity, and (3) it must contribute minimally to device capacitance. 

The pinhole density of polyimide was assessed by a statistical evaluation of shorts using an TiWAu - polyimide - TlWAu multilevel structure where each die contained 3275 crossovers of first and second metal. The probability of good crossovers was taken as... 

Low Interlayer Capacitance. A multilevel structure consisting of a metal-dlelectric-metal sandwich is a capacitor whose capacitance is determined by the dielectric constant and total charge of the dielectric. 

With the increase of the degree of integration of microcircuits, the multilevel interconnect technology becomes inevitable for future VLSI manufacture. Polyimide exhibits superior planarity over stepped structures and is expected to be one of the most promising materials for the dielectric insulation of VLSI s. However, since the smallest via holes so far achieved by wet etching is 3 pm (1), the formation of fine via holes by a dry etch process is needed for the application of polyimide to VLSI having fine metal wiring. 

In inlaid logic devices there is a move away from oxide to metal CMP for more levels of build. However, the process control required for the oxide/W polish levels is tighter because of the requirement of a high degree of planarity from the upper inlaid metal layers. For Cu, a tight polish window with controlled over/under polish has to be maintained at all metal levels for a successful multilevel structure build. 

Prior to the introduction of Cu electroplating, the primary method used to form a multilevel structure of interconnections in integrated circuit applications was A1 and Al-alloy metallization.49 Localized porous-type anodization was developed in the 1970s to obtain planar interconnection metallization for multilevel large-scale integration (LSI) 26,46,50 For example, Schwartz and Platter showed that the subtractive etching for A1 interconnects could be substituted... 

The resulting multilevel structure comprises a series of planar metallic layers with metal inlays in the dielectric, forming the circuitry (see Fig. 16.20). Figures 16.21 and 16.22 show SEM micrographs of a cross section of a 90-nm technology node AMD microprocessor, with nine copper metal layers, fabricated with dual damascene copper interconnect technology. 

Moy, D., et al, 1989. A two-level metal fully planarized interconnect structure Implemented on A 64 KB CMOS SRAM. Santa Clara, CA, USA. In Proceedings of Sixth International IEEE VLSI Multilevel Interconnection Conference, pp. 26—32. 

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