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Chemical mechanical planarization process

A. Hu, X. Zhang, E. Sachs, P. Renteln, Application of Run by Run Controller to the Chemical-Mechanical Planarization Process, IEEE Proceeding of the 15th International... [Pg.44]

D. Bramano and L. Racz Numerical Flow-Visualization of Slurry in a Chemical Mechanical Planarization Process, Proc. of CMP-MIC, pp. 185-192, Santa Clara, CA, Feb. 1998. [Pg.133]

Why is tribology important for the chemical-mechanical planarization process ... [Pg.118]

Treichel H, Frausto R, Srivastan S, Whithers B. Process optimization of dielectrics chemical-mechanical planarization processes for ultralarge scale integration multilevel metallization. J Vac Sci Technol A 1999 17.4 1160-1167. [Pg.559]

H.C. Hong, K.H. Liu, Method for Monitoring the Polishing Pad Used in Chemical-Mechanical Planarization Process, 2001 (US Patent 6194231 Bl). [Pg.356]

Zhang, R, Busnaina, A. A., Reng, J., and Rury, M. A., Particle Adhesion Force in CMP and Subsequent Cleaning Processes," Proceedings, 4th International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference, Santa Clara, CA, Reb. 11-12,1999, pp. 61-64. [Pg.268]

The acceptance of chemical mechanical planarization (CMP) as a manufacturable process for state-of-the-art interconnect technology has made it possible to rely on CMP technology for numerous semiconductor manufacturing process applications. These applications include shallow trench isolation (STI), deep trench capacitors, local tungsten interconnects, inter-level-dielectric (ILD) planarization, and copper damascene. In this chapter. [Pg.5]

B. Withers, E. Zhoa, R. Jairath, A Wide Margin CMP and Clean Process for Shallow Trench Isolation Applications, 1998 Proceedings of the Third International Chemical-Mechanical Planarization for VLSI Multilevel Interconnection Conference (CMP-MIC), Santa Clara, CA, pp. 319-327, Feb. 19-20,1998. [Pg.42]

A. Hu, R. Chan, S. Chiao, Real Time Control of Chemical Mechanical Planarization (CMP) Process, First International Chemical-Mechanical Polish (CMP) for VLSI Multilevel Interconnection Conference, pp. 235-240, Feb. 22-23, 1996. [Pg.45]

As the integrated circuit (IC) industry has chosen chemical mechanical planarization (CMP) as one of the indispensable processes in the generations of transistor gate lengths equal to or smaller than 0.35/im, it is imperative that the CMP-related process problems be investigated and... [Pg.245]

Roy SR, Ali I, Shinn G, Furusawa N, Shah R, Peterman S, Witt K, Eastman S. Post chemical-mechanical planarization cleanup process for interlayer dielectric films. ECS 1995 312(l) 216-226. [Pg.367]

Chatterjee A, Kwok SP, Ali I, Joyner K, Shinn G, Chen I-C. Chemical mechanical planarization (CMP) process windows in shallow trench isolation for advanced CMOS. Electrochem Soc Proc 1996 96-22 219-227. [Pg.367]

This chapter gives an overview of the defects that can be generated or revealed during chemical-mechanical planarization (CMP). Most defects are specific to the type of CMP operation the wafer has just experienced. For this and other obvious reasons, this chapter is organized by CMP applications. However, there are some families of defects that are common to most CMP processes. Indeed, scratches [1-5], remaining particles [6], and surface residues [7] could be found in all CMP applications. Therefore, the materials are presented in the order of complexity, from the simplest such as oxide CMP to the most sophisticated such as copper CMP. Almost all defects presented in oxide CMP could exist in the other applications such as poly-Si, W CMP, and Cu CMP. [Pg.511]

Lin CF, Tseng W, Fengand M, Wang Y. A ULSI shallow trench isolation process through the integration of multilayered dielectric process and chemical-mechanical planarization. Thin Solid Films 1999 22 248-252. [Pg.559]

Nanoceramic Particulates for Chemical Mechanical Planarization in the Ultra Large Scale Integration Fabrication Process... [Pg.176]

Chemical-Mechanical Planarization involves often-conflicting requirements at various length scales—e.g. uniform removal at the wafer scale, but non-uniform removal of high areas to achieve planarization at the feature scale. In conjunction with machine process controls, the management of pressure by the consumables is one key to balancing these requirements. [Pg.51]

Polish time fluctuations are common occurrences in any Chemical Mechanical Planarization (CMP) process. CMP removal rates are affected by many factors such as pattern density, slurry condition, pad condition and polishing parameters such as down pressures and rotation rates. Historical CMP recipes have been based on time with separate recipes for contact and via layers. The Luxtron Real-Time Controller (LRTC) system provided the capability to use endpoint methodology to manage end-of-process versus fixed time recipes. [Pg.109]

J. Schlueter, I. Kim, F. J. Krupa, The Effect of Consumables in the Development of Advanced Shallow Trench Isolation (STI) CMP Processes, Proceedings of Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference (CMP-MIC), 1999, pp.336-339... [Pg.231]


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See also in sourсe #XX -- [ Pg.154 ]




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