Copper interconnect

Researchers in Japan have determined that copper interconnects deposited by metallo-organic chemical vapor deposition (MOCVD), then followed by chemical mechanical polishing, provides sub-quarter-micron interconnects and can be achieved on a production basis. Titanium nitride and borophosphosilicate glass provide effective barriers against copper diffusion.PL[H]... 

Anaya, N., et al., Copper Interconnection Technology for Silicon Large Scale Integrated Circuits,""NTTR D, 45(4) 373-8 (1996)... 

Damacene (Al,Cu) or copper interconnects Tungsten plugs - n Type silicon... 

It may be considered a fortunate coincidence that this book is published at the time of the introduction of copper interconnection technology in the microelectronics industry. In 1998 the major electronic manufacturers of integrated circuits (ICs) are switching from aluminum conductors produced by physical methods (evaporation) to copper conductors manufactured by electrochemical methods (electrodeposition). This revolutionary change from physical to electrochemical techniques in the production of microconductors on silicon is bound to generate an increased interest and an urgent need for familiarity with the fundamentals of electrochemical deposition. This book should be of great help in this crucial time. 

D. T. Price, R. J. Gutmann, S. P. Murarka, Damascene copper interconnects with polymer ILDs, J. Thin Solid Films, 308-309, pp. 523-528, 1997. 

Reexamination of bulk and wafer-level modeling in the context of copper CMP is also underway. Due to the strong interaction between chemical and mechanical processes in copper polishing, consideration of the removal mechanisms as well as proper Preston-equation like modeling is being pursued [37,65]. More work is needed to produce effective and efficient wafer-level, feature-level, and die-level models for copper CMP, particularly as the industry moves to copper interconnect systems. 

For future high-speed microelectronic devices, copper interconnection with low dielectric constant (low-k) interlayer films is required to decrease RC (R interconnect resistance, C interlayer dielectric capacitance) delay. Recently, porous Si02 and silica-based films, developed for low-k films, have been extensively studied by positron annihilation spectroscopy [28], [29], [19]. Since Ps formation occurs with high probability, and the o-Ps annihilate via pick-off process in Si02-based materials, positron annihilation spectroscopy (especially PALS) gives useful information on the size of the pores. 

The first generation of the interconnect material is aluminum with a resistivity of p = 2.66 pQ cm. One approach to reduce RC delay is to switch to an interconnect material with lower resistivity as indicated by Eq. (1.1). A wide range of metals was considered as a potential candidate in the early 1990s. Gold has excellent resistance to corrosion and electromigration but its conductivity is similar to that of aluminum. Silver has the lowest resistivity (p = 1.59 pQ cm) but poor resistance to corrosion and electromigration. Hence, copper that has a resistivity of 1.67 pO cm and excellent resistance to electromigration was selected. Compared to aluminum, copper has one drawback. It cannot be deposited by RIE. Therefore, a copper interconnect is typically formed via a damascene process in which a pattern is first etched into the dielectric and overfilled with copper. The excess copper above the... 

FIGURE 1.20 Cross section SEM image of a copper interconnect after the removal of overburden copper and before the removal of barrier layer (from Ref. 47). 

Bonding of wafers using direct copper-to-copper interconnections is one of the most well-developed approaches to 3D integration, with Tezzaron producing product prototypes at this time [39-42]. Furthermore, Intel has reported a copper-bonding process compatible with 65-nm technology on 300-mm wafers [37,38]. 

Chen KN, Fan A, Tan CS, Reif R. Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology. IEEE Elect Device Lett 2004 25(1) 2004. 

Chen KN, Tan CS, Reif R. Abnormal contact resistance reduction of bonded copper interconnects in three-dimensional integration during current stressing. Appl Phys Lett 2005 86 (011903) 011903-l-011903-3. 

Ryu C. Microstructure and reliability of copper interconnects. Ph.D. Thesis, Stanford University, 1998. p 100. 

Tadepalli R, Thompson CV. Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits. Proceedings of The IEEE International Interconnect Technology Conference 2003. p 36-38. 

If there was no metallie eontamination in the CMP wastewater, then, generally speaking, the waste eould be discharged directly to the POTW without any environmental issues or concern. This was demonstrated in the early days of semiconductor processing before copper interconnects became the industry standard. Since the introduction of copper processing, a whole new industry that provides waste treatment systems has blossomed. 

One major recent advance in silicon-based semiconductor industry is the development of copper interconnects on chips. This new technology replaces the traditional aluminum or aluminum alloy (e.g. Al—Cu) conductors produced by physical vapor deposition (PVD) with copper conductors manufactured by electrodeposition. Copper has been replacing aluminum since 1999 owing to its low bulk electrical... 

Pavlov, M., Shalyt, E., Bratin, P. and Tench, D.M. (2003) in Copper Interconnects, New Contact Metallurgies, Structure and Low-k Interlevel Dielectrics II,... 

The damascene copper interconnects are produced by electrodeposition of copper onto PVD Cu seed layer. The electrodeposition of copper layer is carried out to fill in vias and trenches and consequently to form the metal interconnects. The bottom-up fill of copper in fine via holes as schematically presented in Fig. 4 has successfully been demonstrated by Wang et al.37 using the electroless deposition process. 

Zhang, Z. Zheng, G. Huang, R. Yang, X. Shao, B. Zong, X. Application of copper interconnect and damascene technology in deep submicronic. Res. Progr. SSE. 2001, 21 (4), 407-414. 

Fig. 10 (A) Sequence of filling of a trench profile for the fabrication of Cu interconnects, (B) a cross-section illustration of a six-level wiring structure, and (C) SEM view of IBM s first-to-market six level copper interconnect technology. (From Ref...

Electrodeposition is a liquid-phase analog of plasma-enhanced CVD, used especially in the formation of copper interconnects. This method employs electrochemical voltages instead of surface temperature to control the growth characteristics. It is however more difficult to model and predict than CVD, because of solvation effects and the relative dearth of experimental methods to examine individual elementary steps in the key reactions. ... 

The clrange from Al to Cu interconnects, mentioned above, required concurrent significant changes in the fabrication process, from metal-RIE to dielectric-RIE (reactive ion etching). The introduction of copper interconnects creates, in addition, new problems in tire fabrication of those intereoimects on chips. The most important of tlrose mentioned briefly above, are the possible diffu-... 

Diffusion barrier layers are an integral part of the fabrication of copper interconnects (Figs. 3 and 4). Barrier films isolate (encapsulate) Cu interconnects from adjacent dielectric materials. The diffusion barriers most studied to date are Ti, and TiN. ... 

Fig. 14.2 SEM photographs of copper interconnects capped with 7.5 nm thick CoWP. Le/i cross section view, Right top view. Ref. [19]...

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