Damascene process

Figure 17.11. Process steps for forming Cu interconnects using the single damascene process (dielectric patterning) (a) planarized substrate (b) dielectric deposition (c) dielectric RIE through photoresist mask (d) etched insulator (e) deposition of diffusion barrier (Ta) and Cu seed layer (/) electrodeposition of Cu into a via (vertical interconnection) ( ) CMP of Cu excess Qi) patterning and deposition of Cu line (wire).

Figure 19.3. Process steps for the dual damascene process (a) deposition of dielectric b) dielectric RIE to define via and line (c) deposition of diffusion barrier and Cu seed iayer (d) eiectrodeposition of Cu into via and trenches foiiowed by Cu CMP.

The second definition of the purpose of a carrier was to remove the overburden of material above a surface above the device plane. For present purposes, we define the device level as the boundary between the material one wishes to remove and the material one wants to keep. It is not necessarily planar, and it moves up with each layer. For oxide CMP, this layer lies within the topmost film layer. For metal CMP, this surface is defined by the topmost surface of the dielectric into which lines and vias are etched for a damascene process. This definition must accommodate a wafer with a modest amount of bow, tilt, warp, and total thickness variation. Furthermore, it must accommodate very modest amounts of bow, warp, tilt. 

Local oxide erosion is associated with dishing in damascene process, as discussed in the following. 

The first generation of the interconnect material is aluminum with a resistivity of p = 2.66 pQ cm. One approach to reduce RC delay is to switch to an interconnect material with lower resistivity as indicated by Eq. (1.1). A wide range of metals was considered as a potential candidate in the early 1990s. Gold has excellent resistance to corrosion and electromigration but its conductivity is similar to that of aluminum. Silver has the lowest resistivity (p = 1.59 pQ cm) but poor resistance to corrosion and electromigration. Hence, copper that has a resistivity of 1.67 pO cm and excellent resistance to electromigration was selected. Compared to aluminum, copper has one drawback. It cannot be deposited by RIE. Therefore, a copper interconnect is typically formed via a damascene process in which a pattern is first etched into the dielectric and overfilled with copper. The excess copper above the... 

A typical piece of jewelry made with a damascene process (from... 

Other than the damascene process, is there any other way to form microstructures such as copper lines, tungsten vias, and STI ... 

Layers Typical materials for which CMP processes originally have been developed for microelectronic applications include various types of silicon dioxide such as thermal oxide, TEOS, HDP, BPSG, and other B- or P-doped oxide films. These films are used for various isolation purposes including interlevel dielectric (ILD), intermetal dielectric (IMD), or shallow trench isolation (STI). In addition, n- or p-doped poly-Si, which is a semiconducting material used as capacitor electrode material for DRAMS or gate electrode for MOS applications (CMOS as well as power MOS devices), also has to be polished. Metals for which CMP processes have emerged over the last 10-15 years are W for vertical interconnects (vias) and most importantly Cu as a low-resistivity replacement for aluminum interconnects, employed in the damascene or dual-damascene processing scheme. Other metals that are required for future nonvolatile memories are noble metals like Pt or Ir for which CMP processes have been explored. 

To this point we have discussed recent model extensions in the context of oxide CMP. As illustrated schematically in Fig. 1, dishing and erosion concerns in copper damascene processing also... 

Fig. 36 Process steps for forming Cu interconnects using single damascene process (dielectric patterning) (a) substrate, (b) dielectric deposition,...

One important difference between the damascene and the plating through mask procedures is the way the trenches and vias are filled with electrochemically deposited Cu, either tlirough electro or electroless techniques. In multi-level metal slruclures. the vias provide paths for connecting two conductive regions separated by inter-level dielectric (ILD). In a damascene process the Cu deposit grows from the active bottom and the sidewalls, as shown in Fig. 7a. 

The top and the bottom coils were fabricated using a damascene process. Coil trenches were formed in a SiO insulating layer using reactive ion etching. A seed layer for electrodeposition such as a Cu/Ti stacked layer was sputter-deposited onto the etched surface. Then, the Cu electrically conductive material was electrodeposited on the seed layer using generic copper sulfate solution. Finally, lapping was performed... 

Fig. 15.1 Comparison of subtractive etching process and damascene process...

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