Wafer-level

FIGURE 15.3 Die-on-wafer approach to 3D integration demonstrated by Markunas (Ref. 25) and Tong et al. (Ref 23). (a) A die pick-and-place machine populates a metallized wafer, (b) Cross section of stacked die on wafer-level interconnect. 

Another approach to 3D integration is to use wafer bonding to stack die before singulation this approach is referred to as wafer-level 3D. There have been a variety of approaches to wafer-level 3D that have been demonstrated, which can be categorized by the wafer-bonding approach used oxide-to-oxide, copper-to-copper, polymer-to-polymer (or adhesive bonding), and mixtures of these approaches (such as redistribution layer bonding). Each of these four approaches will be introduced in this section, with emphasis placed on their application to 3D. The bond unit processes are described further in Section 15.4.2, and their associated CMP issues are discussed in detail in Section 15.5. 

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Heat transfer was accomplished by guiding flows through different wafer levels, some acting as energy source, others as heat sink. For cooling, circulating liquids were applied. 

The chips have not to be bonded before the layer deposition, and the droplet deposition and annealing can be performed on wafer level, which is advantageous for device commercialisation. 

Mixed-frequency deposition of the nitride is one possibility to adjust the stress in the deposited layer [122]. The ratio of the deposition times in the high-frequency (375 kHz) and low-frequency (187.5 kHz) plasma can be varied during the process. For the layer used here 95% high-frequency deposition time was chosen (Fig. 4.14e).The stress was measured on wafer-level with a thin-film stress analyzer. The stress value was determined by recording the curvature of the wafer after thin-film deposition. A tensile stress of 75 5 MPa was measured for the layer. 

The first device was a circular-shape microhotplate, which essentially consisted of CMOS-process materials (Sect. 4.1). The fabrication of this microhotplate required a minimum of post-CMOS processing steps. The electrochemical etching process used for the membrane release and the formation of the circular-shape Si island was optimized and can now be routinely apphed on wafer-level. 

Preston s equation indicates a pressure dependency and if the pressure distribution across the surface of the wafer is not uniform, one expects a wafer-level removal rate dependency. Runnels et al, for example, report a model incorporating pressure dependencies to account for wafer scale nonuniformity [42]. The distribution of applied force across the surface of the wafer is highly dependent on the wafer carrier design, and significant innovation in head design to achieve either uniform or controllable pressure distributions is an important area of development. 

A related issue has to do with the initial wafer-level uniformity (wafer thickness, wafer warp and bow, thicknesses of thin films across the wafer surface, uniformity of stress in such thin films across the wafer) and the subsequent impact on wafer-level polish performance. Some examination has been made of the impact of wafer warp and bow on the polish performance [68], where it was found that the initial warpage can have significant impact (with the implication that reclaimed wafers may not be appropriate monitors of wafer-level polish performance). Other work has considered inherent variation due to Von Mises stress concentrations at the edge of the wafer (conceptually, a downward pressure on the wafer causes lateral stress buildup near the edge of the wafer) [64]. 

A number of additional wafer-level variations in the removal rate may result from the variation in the Preston coefficient across the surface of the wafer. Because depends on the slurry, pad, material, and process parameters in a poorly understood fashion, it is not clear where all of these dependencies ultimately reside. 

The modeling of wafer-level polishing effects has primarily been done in the context of blanket wafers with a uniform (unpatterned) single material thin film, and that modeling is usually considered independently of the... 

The desire to improve wafer-level uniformity continues to drive the study of wafer-scale CMP dependencies. Effective and practical means now exist for empirical simulation of wafer-level polish rate across the entire wafer however, substantial enhancement remains necessary to develop predicitive models with sufficient detail and physical bases for exploratory tool design and optimization. 

Reexamination of bulk and wafer-level modeling in the context of copper CMP is also underway. Due to the strong interaction between chemical and mechanical processes in copper polishing, consideration of the removal mechanisms as well as proper Preston-equation like modeling is being pursued [37,65]. More work is needed to produce effective and efficient wafer-level, feature-level, and die-level models for copper CMP, particularly as the industry moves to copper interconnect systems. 

It is now possible to model the wafer-level performance for most CMP processes. These models cover only some of the important tool or process design issues, such as relative velocities and pressure dependencies additional work is needed to predict the results for other parameters such as slurry composition or particle size, temperature dependencies, pad properties, and other effects. Die-level modeling has been used effectively to identify... 

As understanding of the CMP process improves, one can expect a great deal of work in all aspects of CMP modeling and simulation. These improvements are likely to extend over many length scales spanning wafer-level polish and uniformity concerns to die-level prediction to microscopic feature, chemical, and mechanical interactions. 

ITECHNICAL REFERENCE Wafer-Level Ultra-Chio-Scate Package Mfrs of Support... 

Lu J-Q, Rajagopalan G, Gupta M, Cale TS, Gutmann RJ. Planarization issues in wafer-level three-dimensional (3D) integration. MRS Symp Proc 2004 816 217-228. 

Approaches to 3D integration are often divided into die-level approaches and wafer-level approaches. Most often, the heterogeneous integration and small form factor advantages are obtained with die-level approaches in addition, high performance and low manufacturing cost can be achieved with wafer-level approaches. 

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