Bare die

Further miniaturization is enabled by direct assembly of bare dies onto circuit carriers. This kind of component is electrically connected by wire bonding. Other methods for direct chip attachment are flip chip and tape automated bonding. All three methods require special equipment for processing and inspection. 

Bare die and other chip devices are attached with electrically conductive or nonconductive adhesives to ceramic substrates having defined circuit patterns produced by thin-film vapor deposition and photoetching of metals or by screen-printing and firing of thick-film pastes. With recent advancements in fine-line printed-circuit boards, adhesives are also finding use in attaching bare die to PWBs, a technology known as chip-on-board (COB). 

After mechanical attachment to a substrate, a leadframe, or to the inside of a package, bare die or chip devices are electrically connected by one of five methods wire bonding, flip-chip bonding, TAB, solder attachment, or attachment with electrically conductive adhesives. Fig. 1.6 shows some of these methods. 

Bare die such as integrated circuits may be assembled in plastic or ceramic carriers, called chip-scale packages, whose dimensions are slightly larger than the chip. CSPs are often defined as packages that are no larger than 1.5 times the area of the die or no more than 1.2 times the width or length of the die. If the carrier is a BGA type, an alternate definition is that the solder-ball pitch be less than 1 mm. The pitch of... 

After the adhesive has been dispensed onto the PCBs or other interconnect substrate, bare die and other electronic components must be precisely placed. Of course, pick and place can be done manually using vacuum pick-up tools or tweezers, but this approach is useful only for small quantities, prototypes, or for rework. The risk of... 

Some adhesive materials and processes are used across many apphcations. For example, adhesives are used to attach bare die, components, and substrates in assembling commercial, consumer and aerospace electronic products. Adhesives are also widely used for surface mounting components onto interconnect substrates that serve numerous functions for both low-end consumer products and for high rehability applications. Underfill adhesives are used to provide stress relief and ruggedize the solder interconnects for almost all flip-chip and area-array devices, regardless of their function as integrated circuits. 

Some adhesive materials and processes are used across many applications. For example, adhesives used to attach bare die and substrates in hybrid or multichip modules may be used for a wide variety of ground-based military... 

Bare Die Through-Hole Packages Module Assemblies... 

The test technology used to ensure correct function of the bare die, the MCM substrate, and the assembled MCM. 

An important adjunct to the physical technology is the technology required to test and repair the die and modules. An important question that has to be answered for every MCM is how much to test the die before assembly vs. how much to rely on postassembly test to locate failed die. This is purely a cost question. The more the bare die are tested, the more likely that the assembled MCM will work. If the assembled MCM does not work, then it must either be repaired (by replacing a die) or discarded. The question reduces to the one that asks what level of bare die test provides a sufficiently high confidence that the assembled MCM will work, or is the assembled module cheap enough to throw away is a die is faulty. 

In general, there are four levels of bare die test and burn-in, referred to as four levels of known good die (KGD). In Table 8.10, these test levels are summarized, along with their impact. The lowest KGD level is to just use the same tests normally done at wafer level, referred to as the wafer sort tests. Here the chips are normally subject to a low-speed functional test combined with some parametric measurements (e.g., measurement of transistor curves). With this KGD level, test costs for bare die are limited to wafer test costs only. There is some risk, however, that the chip will not work when tested as part of the MCM. This risk is measured as the test escape rate. With conventional packaging, the chips are tested again, perhaps at full speed, once they are packaged, making the test escape rate zero. 

The most important issue in the design of multichip modules is obtaining bare die. The first questions to be addressed in any MCM project are the questions as to whether the required bare die are available in the quantities required, with the appropriate test level, with second sourcing, at the right price, etc. Obtaining answers to these questions is time consuming as many chip manufacturers stiU see their bare die sales as satisfying a niche market. If the manufactured die are not properly available, then it is important to address alternative chip sources early. 

The use of bare die in chip on board (COB) and multichip module (MCM) apphcations is increasing with designers looking for end item size and weight reduction (automotive applications have bond wires going directly from the die to a connector). The use of bare die eliminates the timing delays (caused by stray inductance and capacitance) associated with the leadfi ames and the device input/outputs (1/Os). For burst mode static RAMs, 1/2-2 ns or a 20% improvement in access time is achieved with bare die product. Small portable devices can also use flip-chip bonding. 

In addition to bare die and surface mount techniques, there are still the older device packages for through-hole applications, where the lead of the package goes through the printed wiring board (see Fig. 8.128 and Fig. 8.129). Modules are also available that are assemblies of either packaged parts or die. 

Micro SMT, a peripheral contact package formed using semiconductor fabrication techniques while the IG is in wafer form. This technology was developed by GhipScale, Inc. (San Jose, GA). The resulting device is not much larger than the bare die. 

In the most fundamental configuration, the semiconductor die is taken directly from the wafer without further processing (generally referred to as a bare die). In this process, the die is mechanically mounted to the substrate with epoxy, solder, or by direct eutectic bonding of the sihcon to the substrate metallization, and the electrical connections are made by bonding small wires from the bonding pads to the appropriate conductor. This is referred to as chip-and-wire technology, illustrated in Fig. 11.10. 

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