Wafer electrical test

The wafer is tested twice to determine yield—once after the deposition of the first metal (referred to as in-line parameteric testing) and again after the completion of the last fabrication process (referred to as wafer sort). The first test is also referred to as the wafer electrical test (WET) and is performed in line. In the last test, each die on the wafer is tested for electrical functionality, and the obtained data is used to compute the die yield. 

Here, it is easy to see the various layers and steps necessary to form the IC. We have already emphasized the formation of the n- and p-wells 8uid the individual proeess steps needed for their formation. Note that an epitaxial layer is used in the above model. There are isolation barriers present which we have already discussed. However, once the polysilicon gate transistors are formed, then metal Interconnects must then be placed in proper position with proper electrical isolation. This is the function of the dielectric layers put into place as succeeding layers on the IC dice. Once this is done, then the wafer is tested. 

The only way to obtain all necessary parameters is to apply model-based measurement techniques and electrical stimulation during wafer-level tests for each single device or by using test structures designed especially to obtain in-process measurement data (see [28, 29] and Section 5.10). This requires that the sensor s behavior is well understood and the dependencies of the various parameters can be expressed analytically according to Eq. 4.3. 

Electrical test. An automatic, computer-driven electrical test system then checks the functionality of each chip on the wafer. Chips that do not pass the test are marked with red ink for rejection. 

Lowest cost of electrical testing, as this is done at the wafer level... 

Fig. 4.5a-c Rectangular micro-channels, (a) 4i = 133—367 pm. Test section used by Peng and Peterson (1996) (schematic view) 1 electrical contact, 2 heated stainless steel block, 5 micro-channel, 4 cover plate, (b) <4 = 404—1,923 pm. Test section used by Harms et al. (1999) (schematic view) 1 silicon wafer, 2 micro-channel, 3 heater, 4 cover plate, (c) dh = 348 pm. Test section used by Qu and Mudawar (2002a) (schematic view) 1 copper block, 2 micro-channel, 3 heater, 4 cover plate. Reprinted from Peng and Peterson (1996), Harms et al. (1999), Warrier et al. (2002), Qu and Mudawar (2002a), Gao et al. (2002), and Lee et al. (2005) with permission... 

As illustrated in Fig. 15.11, wafers can be bonded face-to-face, the handle of the SOI wafer can be thinned to stop on the buried oxide layer, rebonded to another handle wafer, thinned again to stop on the bonding layer, and then tested. Lu et al. have used this approach to demonstrate process compatibility on passive structures [85], Gutmann et al. have used this method to demonstrate process compatibility using active electrical structures [49], and... 

The purpose of this study was to explore the interaction between slurry particles and wafer surfaces by the measurements of their zeta potentials. The zeta potentials of slurry particles such as fumed and colloidal silica, alumina, ceria and MnOj and substrates such as silicon, TEGS, W, and A1 have been measured by electrophoretic and electroosmosis method to evaluate the electrical properties of surfaces, respectively. The zeta potential of oxide and metal surfaces showed similar values to those of particles as a function of pH. The interaction energy between alumina and silica particles and TEOS, W and A1 substrate were calculated based on DLVO theory. No deposition of silica particles on TEOS and the heavy deposition of alumina particles on metal substrates were observed in the particle deposition test. Experimental results were well agreed with the theoretical calculation. 

Figure 3.9. Electrical probe yield of meander patterns versus design feature size and wavelength. The vertical bars indicate the total yield range for the wafer tested. (Reproduced with permission from reference 23.)...

When a built-in self test is not feasible, we encounter difficulties because primary input signals cannot be easily provided within a standardized probe setup. To our knowledge, no commercial testing equipment is available that allows a set of primary stimuli like acceleration, pressure, torque, or mass flow to be applied to the transducer elements of sensor chips on the wafer level, with the required speed and precision. At the moment we are therefore left with purely electrical stimuli for testing microsensor devices. 

Concurrently design test structures and develop test models dedicated solely to extracting critical model parameters from electrical precision measurements on the wafer level. Improve fabrication processes using test structures early in the sensor development phase and well in advance of starting production. Eventually, reduce the number of test structures and the wafer space they occupy, optimize testing time and equipment, and then commit a test setup to production. 

At the end of the wafer processing, the wafer with the IC devices is inspected for defects and reviewed with relevant metrology. If the defect level is acceptable, the IC wafer is sent to the testing facility, where it is electrically probed to check for electrical performance. Next, the IC wafer is stress tested, which involves operating it at the extremes of its specified typical use conditions. If the IC wafer passes the functional and stress tests, it is sent to the packaging facility, where bond pad... 

Electrical measurement of the dielectric constant is done through the fabrication of metal—oxide—semiconductor capacitor structures, where the ULK serves as the dielectric of the capacitor. A doped Si wafer is used as the substrate, on which the ULK film is deposited. This ULK film is subjected to CMP, say, or any other process whose impact on ULK characteristics needs to be quantified. An aluminum film is deposited on the backside of the Si wafer to form one of the capacitor contacts. Using a shadow mask, aluminum dots of varying diameters are evaporated onto the surface of the ULK film, to form the other terminal of the capacitor. Each aluminum dot is probed to measure its capacitance (at about 100 kHz). Evaporation through a shadow mask allows for the formation of metal contacts without altering the dielectric further— as would be the case if reactive-ion-etch were used to form the contacts. (It should be noted that more complex process flows can be used to eliminate concerns such as dot-size variation, the effect of probe-tip impact on the dielectric being tested, etc.) The results of electrical measurement of the k-value increase post-CMP of the variety... 

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